From nobody Wed Dec 17 15:43:06 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF1E6226CE1; Mon, 17 Mar 2025 10:34:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742207652; cv=none; b=ilrMO9nKyfdf1fEj+0sqX62ROc3Qww68psxrY5OKKK+WqEDoPmLxi88LGdqp7MBkhzPRqDoYjbWSxtDF8uDssLynoMUNj5xvvE0cTE6QwDgbn/OS26yuuKfIYkyEu7ItWMzCNfpCM7EmKSbC2z4KNECfhzlJLO/d1VLmtoka4RM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742207652; c=relaxed/simple; bh=S4cTUlJOdMP3rdiOpfmbGih8e8KS4EqCixiznUITXMo=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=ACGv6jvE6GisgI7Xfzqw6l2pJS3EwALsdSOOx68ynD/YI64tZO3dlGczFgZfce8t6qxFLh7CJKFsqqdUYVUPL61XV9rFl4Lm0Q6P6aQ4+E1OHkMJ4IkqcZRtSd9wI96TSlueBLCjZIOQ9s3by1KuO2jzfbXQ21Is8W86DAuYGI0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=uX0gFqbS; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MjsUW+9r; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="uX0gFqbS"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MjsUW+9r" Date: Mon, 17 Mar 2025 10:34:08 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1742207649; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Txr8vJhJnuznKko/E5p0Eb5kklDmzfkiEhlhLEIVSDY=; b=uX0gFqbS9R5bRSR2wjLWojGOrFivuGCalLs96hJeYnkUc+fuYYqmzh26/f0OgOeev1ZClY hphbG5HlCF7RFD6hNRX0oPikzsH8khgEdi99nMaRVjIGPPrUaIdWeAmJo6pn82wYp0KKYD p3/nwh0ubOM83n+7Ps9m+Z6ezbkMTlC0xU3eipbGAACTnSnZ4E/+5hqitqA2YQgbpDe3BG rKyyQtJGym23BoUzV/pGp6mMrK6nIjgtRksBBztx4YAe7UjK/ur5M872kWAFZELAW+lFy0 o/mpjSJP83hu1BJMVxz9VXJei5pJA1SAUJ9X5Jiy84Dwz+516YEM/xIdH3gYsg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1742207649; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Txr8vJhJnuznKko/E5p0Eb5kklDmzfkiEhlhLEIVSDY=; b=MjsUW+9rc33uUC76K4+yCVNFOkojKISW0b3lMI5uGNCMIsfKVRWdTft3VM7n7o4sktrEXr UkdytNxaXE8qw3Aw== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/lbr: Fix shorter LBRs call stacks for the system-wide mode Cc: Andi Kleen , Alexey Budankov , Kan Liang , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250314172700.438923-5-kan.liang@linux.intel.com> References: <20250314172700.438923-5-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174220764858.14745.11451017653270864906.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 3cec9fd03543c1e2919f906353e5cba079ae0a7c Gitweb: https://git.kernel.org/tip/3cec9fd03543c1e2919f906353e5cba07= 9ae0a7c Author: Kan Liang AuthorDate: Fri, 14 Mar 2025 10:26:58 -07:00 Committer: Peter Zijlstra CommitterDate: Mon, 17 Mar 2025 11:23:37 +01:00 perf/x86/lbr: Fix shorter LBRs call stacks for the system-wide mode In the system-wide mode, LBR callstacks are shorter in comparison to the per-process mode. LBR MSRs are reset during a context switch in the system-wide mode. For the LBR call stack, the LBRs should be always saved/restored during a context switch. Use the space in task_struct to save/restore the LBR call stack data. For a system-wide event, it's unnecessagy to update the lbr_callstack_users for each threads. Add a variable in x86_pmu to indicate whether the system-wide event is active. Fixes: 76cb2c617f12 ("perf/x86/intel: Save/restore LBR stack during context= switch") Reported-by: Andi Kleen Reported-by: Alexey Budankov Debugged-by: Alexey Budankov Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20250314172700.438923-5-kan.liang@linux.int= el.com --- arch/x86/events/intel/lbr.c | 47 +++++++++++++++++++++++++++++------ arch/x86/events/perf_event.h | 1 +- 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index dafeee2..24719ad 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -422,11 +422,17 @@ static __always_inline bool lbr_is_reset_in_cstate(vo= id *ctx) return !rdlbr_from(((struct x86_perf_task_context *)ctx)->tos, NULL); } =20 +static inline bool has_lbr_callstack_users(void *ctx) +{ + return task_context_opt(ctx)->lbr_callstack_users || + x86_pmu.lbr_callstack_users; +} + static void __intel_pmu_lbr_restore(void *ctx) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); =20 - if (task_context_opt(ctx)->lbr_callstack_users =3D=3D 0 || + if (!has_lbr_callstack_users(ctx) || task_context_opt(ctx)->lbr_stack_state =3D=3D LBR_NONE) { intel_pmu_lbr_reset(); return; @@ -503,7 +509,7 @@ static void __intel_pmu_lbr_save(void *ctx) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); =20 - if (task_context_opt(ctx)->lbr_callstack_users =3D=3D 0) { + if (!has_lbr_callstack_users(ctx)) { task_context_opt(ctx)->lbr_stack_state =3D LBR_NONE; return; } @@ -543,6 +549,7 @@ void intel_pmu_lbr_sched_task(struct perf_event_pmu_con= text *pmu_ctx, struct task_struct *task, bool sched_in) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); + struct perf_ctx_data *ctx_data; void *task_ctx; =20 if (!cpuc->lbr_users) @@ -553,14 +560,18 @@ void intel_pmu_lbr_sched_task(struct perf_event_pmu_c= ontext *pmu_ctx, * the task was scheduled out, restore the stack. Otherwise flush * the LBR stack. */ - task_ctx =3D pmu_ctx ? pmu_ctx->task_ctx_data : NULL; + rcu_read_lock(); + ctx_data =3D rcu_dereference(task->perf_ctx_data); + task_ctx =3D ctx_data ? ctx_data->data : NULL; if (task_ctx) { if (sched_in) __intel_pmu_lbr_restore(task_ctx); else __intel_pmu_lbr_save(task_ctx); + rcu_read_unlock(); return; } + rcu_read_unlock(); =20 /* * Since a context switch can flip the address space and LBR entries @@ -589,9 +600,19 @@ void intel_pmu_lbr_add(struct perf_event *event) =20 cpuc->br_sel =3D event->hw.branch_reg.reg; =20 - if (branch_user_callstack(cpuc->br_sel) && event->pmu_ctx->task_ctx_data) - task_context_opt(event->pmu_ctx->task_ctx_data)->lbr_callstack_users++; + if (branch_user_callstack(cpuc->br_sel)) { + if (event->attach_state & PERF_ATTACH_TASK) { + struct task_struct *task =3D event->hw.target; + struct perf_ctx_data *ctx_data; =20 + rcu_read_lock(); + ctx_data =3D rcu_dereference(task->perf_ctx_data); + if (ctx_data) + task_context_opt(ctx_data->data)->lbr_callstack_users++; + rcu_read_unlock(); + } else + x86_pmu.lbr_callstack_users++; + } /* * Request pmu::sched_task() callback, which will fire inside the * regular perf event scheduling, so that call will: @@ -665,9 +686,19 @@ void intel_pmu_lbr_del(struct perf_event *event) if (!x86_pmu.lbr_nr) return; =20 - if (branch_user_callstack(cpuc->br_sel) && - event->pmu_ctx->task_ctx_data) - task_context_opt(event->pmu_ctx->task_ctx_data)->lbr_callstack_users--; + if (branch_user_callstack(cpuc->br_sel)) { + if (event->attach_state & PERF_ATTACH_TASK) { + struct task_struct *task =3D event->hw.target; + struct perf_ctx_data *ctx_data; + + rcu_read_lock(); + ctx_data =3D rcu_dereference(task->perf_ctx_data); + if (ctx_data) + task_context_opt(ctx_data->data)->lbr_callstack_users--; + rcu_read_unlock(); + } else + x86_pmu.lbr_callstack_users--; + } =20 if (event->hw.flags & PERF_X86_EVENT_LBR_SELECT) cpuc->lbr_select =3D 0; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 0d5019f..67d2d25 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -920,6 +920,7 @@ struct x86_pmu { const int *lbr_sel_map; /* lbr_select mappings */ int *lbr_ctl_map; /* LBR_CTL mappings */ }; + u64 lbr_callstack_users; /* lbr callstack system wide users */ bool lbr_double_abort; /* duplicated lbr aborts */ bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */