From nobody Tue Dec 16 16:03:23 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 020142010EE; Fri, 21 Feb 2025 09:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740128497; cv=none; b=TYyj/wN/LjzqnBzr9kI+DYHsqTNDmOJJX2Ws72xLLZV+Oqe9kPKe00XU5m9W3rpeIM/NBOy5ZBdvJ9RqyRsNcIYnRaFzUosOtNDwQ7vwr3YlOUXswkPuqPpoUo3/H0DTeSMgKXYc1VWW2YPs/M7bOfm/kWPBC4psL/J93Qn06KA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740128497; c=relaxed/simple; bh=8sFCUjI1xq8pRRYYyDQPupuJZGGyAF9bvjsY+J6JXZw=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=sb8irF388gES0c7ZJT5zYZ/uZnBDQL+LYgdkMRa90iGljNBIcNUogxUGnVriLpfrnw5VJMquQPOCUN93Tc5/NVmPtUP/5Im9sHKJlwKibMV15sw0+xEoVn1rLYMoKmFAmNb7KbCSfvRlc8tDTzOw9T178OBoPkzmY7nk7OxqAtE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HhL/O3q1; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=9mXDCiSB; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HhL/O3q1"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="9mXDCiSB" Date: Fri, 21 Feb 2025 09:01:32 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1740128493; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VZK8joqsGzpvbUK9ewl94o6aECCb/BiADE50bbsKHtI=; b=HhL/O3q1FpC26HW9d82HumdQCMHnN8xBSKicy4VZlcaEOO93qY+Y5Ici//xUlCR5pIA74a T+askSAwOdDaUuWAFU2beWCgLkQgWyHZzdPINO9L4vIBvlW+HEXvN4qliYe4KCZsNICFPk 3Q+z5/j4p1RXdnRzZoOoHcZOSJ1iFrZgH0opkGxIRLq+D3bANQFP6RbuwST+HxRtslbjPF oZ5BN1mSDizyadiNmwTNG9S681PaaZkrpzEp8qJX3iSkJSlLtelXCMCStDy49eYsBi2wkZ AQ0qcGUHwqSc/4itDSXc/dXLu1kDkHSD5EBcuOzWUHUHZ+d4OWlEfb+xgEa3rA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1740128493; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VZK8joqsGzpvbUK9ewl94o6aECCb/BiADE50bbsKHtI=; b=9mXDCiSBKPklCPjFDhenLSaQmpY8gyqVMYwBZ/wXJK+rLvkQDF29IJ/X9VS3cadEcpCr1D EujglMy9dkgxg3CA== From: "tip-bot2 for Dmitry Osipenko" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Cc: Dmitry Osipenko , Thomas Gleixner , Marc Zyngier , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250216221634.364158-2-dmitry.osipenko@collabora.com> References: <20250216221634.364158-2-dmitry.osipenko@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174012849254.10177.6166162007500180084.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 2d81e1bb625238d40a686ed909ff3e1abab7556a Gitweb: https://git.kernel.org/tip/2d81e1bb625238d40a686ed909ff3e1ab= ab7556a Author: Dmitry Osipenko AuthorDate: Mon, 17 Feb 2025 01:16:32 +03:00 Committer: Thomas Gleixner CommitterDate: Fri, 21 Feb 2025 09:58:07 +01:00 irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Rockchip RK3566/RK3568 GIC600 integration has DDR addressing limited to the first 32bit of physical address space. Rockchip assigned Erratum ID #3568002 for this issue. Add driver quirk for this Rockchip GIC Erratum. Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is common for many ARM GICv3 implementations. Hence, there is an extra of_machine_is_compatible() check. Signed-off-by: Dmitry Osipenko Signed-off-by: Thomas Gleixner Acked-by: Marc Zyngier Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@c= ollabora.com --- Documentation/arch/arm64/silicon-errata.rst | 2 ++- arch/arm64/Kconfig | 9 ++++++++- drivers/irqchip/irq-gic-v3-its.c | 23 +++++++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index f074f62..f968c13 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -284,6 +284,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_35= 88001 | +----------------+-----------------+-----------------+--------------------= ---------+ +| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_35= 68002 | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010= 001 | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fcdd0ed..0507e47 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1303,6 +1303,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM =20 If unsure, say Y. =20 +config ROCKCHIP_ERRATUM_3568002 + bool "Rockchip 3568002: GIC600 can not access physical addresses higher t= han 4GB" + default y + help + The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI + addressing limited to the first 32bit of physical address space. + + If unsure, say Y. + config ROCKCHIP_ERRATUM_3588001 bool "Rockchip 3588001: GIC600 can not support shareability attributes" default y diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-= its.c index 8c3ec57..f30ed28 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida); #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) =20 +static gfp_t gfp_flags_quirk; + static struct page *its_alloc_pages_node(int node, gfp_t gfp, unsigned int order) { struct page *page; int ret =3D 0; =20 - page =3D alloc_pages_node(node, gfp, order); + page =3D alloc_pages_node(node, gfp | gfp_flags_quirk, order); =20 if (!page) return NULL; @@ -4887,6 +4889,17 @@ static bool __maybe_unused its_enable_quirk_hip09_16= 2100801(void *data) return true; } =20 +static bool __maybe_unused its_enable_rk3568002(void *data) +{ + if (!of_machine_is_compatible("rockchip,rk3566") && + !of_machine_is_compatible("rockchip,rk3568")) + return false; + + gfp_flags_quirk |=3D GFP_DMA32; + + return true; +} + static const struct gic_quirk its_quirks[] =3D { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -4954,6 +4967,14 @@ static const struct gic_quirk its_quirks[] =3D { .property =3D "dma-noncoherent", .init =3D its_set_non_coherent, }, +#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 + { + .desc =3D "ITS: Rockchip erratum RK3568002", + .iidr =3D 0x0201743b, + .mask =3D 0xffffffff, + .init =3D its_enable_rk3568002, + }, +#endif { } };