From nobody Tue Dec 16 11:08:39 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8CEB1FCCF8; Thu, 20 Feb 2025 14:26:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740061604; cv=none; b=KMpQFbWnpgmxQXc2RAbDymj6i+BG0N1CZFNfiDThVKFFc21MmlRNKDyGoudoQZpWfzBXqvipIcuFrAyRqHUaEvAxGGUZXCnsykr1rJMn+OtG3OwDf0SsHQ4U8cEzytPi6UnlT85OQdXyMo9VSXnEdpaP9p5t+HJ8VgeFVciHDw8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740061604; c=relaxed/simple; bh=HeYTR7SfGXAxEpxecbbVFVxFl26KBupYAVriewgewfQ=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=tJE8LSW6c71PmiS6uXaW6tpMeCMWc1EyS/L48RPpKcB4mZq5b0QnYNe8Gesg1QgntF5XHSpdtY9nQFrZNY90TO723e0PlWybIkRre6BnOzQBhX859rMG9WdLYMy8JhxgsMCXq+d0kXH4FZiYup7EnjGncqXzKbUj+ZR4Wb/12RE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=byhhgSVR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=t+6ULUJx; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="byhhgSVR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="t+6ULUJx" Date: Thu, 20 Feb 2025 14:26:40 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1740061601; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NBKVUIcKWtz77kQi0wYkelRbVy8vgV1E+kIc1lll4Js=; b=byhhgSVRruaU9G9SnA4NfPS2sap5c+VDqlms88ZLJZ5BZlof0c3NsqlrVKm8rmJos4bhmZ G2sDzfjFNeVRBNmVh/L9PHRTYxN5oWqBFWAdHHlzgR22pTaQ3LVELHNc/ziuT4DK7plGrv /NaP5ocLWGGAkzIkUVy/caer2QKDEGT3TPqfLQK1Czfzn/EUtFfc4oytLhRNvQmy4Ow894 6tc14pf2Bz6ECwFUp7wgA/ijCxFhe4S19yIZKYwuC3gEseIyaIFzNeSgGz3La1O4fXo/cg S9mgjQuCRiDauqLqiZbqK7vvLTe7XAnMC/BP4zmAQREfe2QEulqigQNWWUd5HQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1740061601; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NBKVUIcKWtz77kQi0wYkelRbVy8vgV1E+kIc1lll4Js=; b=t+6ULUJxdzqRLRYp7YjF1KN1Ojn6U0UYpPX7F1YwBIDN4St0n1dhtsU/EZHEWVeIYwyJK4 vRfmOjFWRrDKIvCg== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/riscv-imsic: Move to common MSI library Cc: Thomas Gleixner , Andrew Jones , Anup Patel , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250217085657.789309-4-apatel@ventanamicro.com> References: <20250217085657.789309-4-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <174006160061.10177.6884394612873814383.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: fe35ecee8ec8d42b1d24ed70e5b33192294bcef0 Gitweb: https://git.kernel.org/tip/fe35ecee8ec8d42b1d24ed70e5b331922= 94bcef0 Author: Thomas Gleixner AuthorDate: Mon, 17 Feb 2025 14:26:49 +05:30 Committer: Thomas Gleixner CommitterDate: Thu, 20 Feb 2025 15:19:26 +01:00 irqchip/riscv-imsic: Move to common MSI library Simplify the leaf MSI domain handling in the RISC-V IMSIC driver by using msi_lib_init_dev_msi_info() and msi_lib_irq_domain_select() provided by the common MSI library. Signed-off-by: Thomas Gleixner Signed-off-by: Andrew Jones Signed-off-by: Anup Patel Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20250217085657.789309-4-apatel@ventanamic= ro.com --- drivers/irqchip/Kconfig | 8 +- drivers/irqchip/irq-riscv-imsic-platform.c | 114 +-------------------- 2 files changed, 6 insertions(+), 116 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index be063bf..bc3f12a 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -589,13 +589,7 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_MATRIX_ALLOCATOR select GENERIC_MSI_IRQ - -config RISCV_IMSIC_PCI - bool - depends on RISCV_IMSIC - depends on PCI - depends on PCI_MSI - default RISCV_IMSIC + select IRQ_MSI_LIB =20 config SIFIVE_PLIC bool diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 5d7c30a..9a5e7b4 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -20,6 +20,7 @@ #include #include =20 +#include "irq-msi-lib.h" #include "irq-riscv-imsic-state.h" =20 static bool imsic_cpu_page_phys(unsigned int cpu, unsigned int guest_index, @@ -174,22 +175,6 @@ static void imsic_irq_domain_free(struct irq_domain *d= omain, unsigned int virq, irq_domain_free_irqs_parent(domain, virq, nr_irqs); } =20 -static int imsic_irq_domain_select(struct irq_domain *domain, struct irq_f= wspec *fwspec, - enum irq_domain_bus_token bus_token) -{ - const struct msi_parent_ops *ops =3D domain->msi_parent_ops; - u32 busmask =3D BIT(bus_token); - - if (fwspec->fwnode !=3D domain->fwnode || fwspec->param_count !=3D 0) - return 0; - - /* Handle pure domain searches */ - if (bus_token =3D=3D ops->bus_select_token) - return 1; - - return !!(ops->bus_select_mask & busmask); -} - #ifdef CONFIG_GENERIC_IRQ_DEBUGFS static void imsic_irq_debug_show(struct seq_file *m, struct irq_domain *d, struct irq_data *irqd, int ind) @@ -206,110 +191,21 @@ static void imsic_irq_debug_show(struct seq_file *m,= struct irq_domain *d, static const struct irq_domain_ops imsic_base_domain_ops =3D { .alloc =3D imsic_irq_domain_alloc, .free =3D imsic_irq_domain_free, - .select =3D imsic_irq_domain_select, + .select =3D msi_lib_irq_domain_select, #ifdef CONFIG_GENERIC_IRQ_DEBUGFS .debug_show =3D imsic_irq_debug_show, #endif }; =20 -#ifdef CONFIG_RISCV_IMSIC_PCI - -static void imsic_pci_mask_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} - -static void imsic_pci_unmask_irq(struct irq_data *d) -{ - irq_chip_unmask_parent(d); - pci_msi_unmask_irq(d); -} - -#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI) - -#else - -#define MATCH_PCI_MSI 0 - -#endif - -static bool imsic_init_dev_msi_info(struct device *dev, - struct irq_domain *domain, - struct irq_domain *real_parent, - struct msi_domain_info *info) -{ - const struct msi_parent_ops *pops =3D real_parent->msi_parent_ops; - - /* MSI parent domain specific settings */ - switch (real_parent->bus_token) { - case DOMAIN_BUS_NEXUS: - if (WARN_ON_ONCE(domain !=3D real_parent)) - return false; -#ifdef CONFIG_SMP - info->chip->irq_set_affinity =3D irq_chip_set_affinity_parent; -#endif - break; - default: - WARN_ON_ONCE(1); - return false; - } - - /* Is the target supported? */ - switch (info->bus_token) { -#ifdef CONFIG_RISCV_IMSIC_PCI - case DOMAIN_BUS_PCI_DEVICE_MSI: - case DOMAIN_BUS_PCI_DEVICE_MSIX: - info->chip->irq_mask =3D imsic_pci_mask_irq; - info->chip->irq_unmask =3D imsic_pci_unmask_irq; - break; -#endif - case DOMAIN_BUS_DEVICE_MSI: - /* - * Per-device MSI should never have any MSI feature bits - * set. It's sole purpose is to create a dumb interrupt - * chip which has a device specific irq_write_msi_msg() - * callback. - */ - if (WARN_ON_ONCE(info->flags)) - return false; - - /* Core managed MSI descriptors */ - info->flags |=3D MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | - MSI_FLAG_FREE_MSI_DESCS; - break; - case DOMAIN_BUS_WIRED_TO_MSI: - break; - default: - WARN_ON_ONCE(1); - return false; - } - - /* Use hierarchial chip operations re-trigger */ - info->chip->irq_retrigger =3D irq_chip_retrigger_hierarchy; - - /* - * Mask out the domain specific MSI feature flags which are not - * supported by the real parent. - */ - info->flags &=3D pops->supported_flags; - - /* Enforce the required flags */ - info->flags |=3D pops->required_flags; - - return true; -} - -#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI) - static const struct msi_parent_ops imsic_msi_parent_ops =3D { .supported_flags =3D MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX, .required_flags =3D MSI_FLAG_USE_DEF_DOM_OPS | - MSI_FLAG_USE_DEF_CHIP_OPS, + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSI_MASK_PARENT, .bus_select_token =3D DOMAIN_BUS_NEXUS, .bus_select_mask =3D MATCH_PCI_MSI | MATCH_PLATFORM_MSI, - .init_dev_msi_info =3D imsic_init_dev_msi_info, + .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 int imsic_irqdomain_init(void)