From nobody Wed Dec 17 08:54:33 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B22A126BD9C; Tue, 11 Feb 2025 15:06:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739286370; cv=none; b=rBaXE+koBVQnDdFJFNqjMaEEqmHfuG3gcHrGdyCqcMYurHYIhrs+/4d1+Nj7ygqD564EP5DV3Ke+nZwByp24roocYgmCfiHUcyCg95KsXySD4ckWRlrn3lL3SfCjOgwA7yqC3Rz2UjzyEjvVj+YMaqrY1W3OuNC/5R38AvVUHlc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739286370; c=relaxed/simple; bh=R/7A2NvhQNEJcZS4cgpl4qGXqNgGP+wzHAKlWlxAIDU=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=PpePYBsOLRhigbO68yGNl34xapJacdq08J68iTF5IffE9qDoPeAdpsnyAMwi5x6HRYaNqc6zPPrQDW2MIntWCkPBKuqic+uPbVOhd97SmOZHx3335uc0I3M3nk1qcdTK1gca6tnvxaE1i5QKeZ+KrwDqdLoA4u3bcOkNnoARVRs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bEsNap3V; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CJ8hnyRs; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bEsNap3V"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CJ8hnyRs" Date: Tue, 11 Feb 2025 15:06:06 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1739286367; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i1fB+4qbBULrKAnQhEvPC9k1uoEJ+L+hYMxA32am+Ww=; b=bEsNap3VkdefPGp1+maLo8k5Wh8ze/e0faO1wHpabz2Ve5Rks6WTrpZ3rpPt2Y6MKwy8eL 9TXWaGZzORLKtGddCjHyLK+hNDyABu7i3HvrKyFrQLysqcBFxiRI54lh/zD4PnGMOWEthV esyCmzUw3HPjpjrYqUvj25OhFyG+N/H/0WPbpJ/7yf9qoOCKGP6sYFlMj56Ui4wHPwnuzS 6MmdgBQKRbNe8qaAh5ZVkdWLwRTt0PLpkbKjsm0E1IffOdlOJiSvWtLjgOwgoaVZdNKoCN em48q6Ywtt0mgomAfgbn+AnVnWtJVyaPCD3+gjnEts8y1Z2b4WlnHc04aU+gCA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1739286367; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i1fB+4qbBULrKAnQhEvPC9k1uoEJ+L+hYMxA32am+Ww=; b=CJ8hnyRsjNNLh0muIun/rESH8LR7QtLdCu3MASALoKNaBdCMv/EnVP/fqI+6W3waE5AEqA KXD7/NRRt+5fUFAg== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/urgent] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF Cc: Kan Liang , "Peter Zijlstra (Intel)" , stable@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20250129154820.3755948-3-kan.liang@linux.intel.com> References: <20250129154820.3755948-3-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <173928636641.10177.8036083101201125379.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/urgent branch of tip: Commit-ID: 47a973fd75639fe80d59f9e1860113bb2a0b112b Gitweb: https://git.kernel.org/tip/47a973fd75639fe80d59f9e1860113bb2= a0b112b Author: Kan Liang AuthorDate: Wed, 29 Jan 2025 07:48:19 -08:00 Committer: Peter Zijlstra CommitterDate: Sat, 08 Feb 2025 15:47:25 +01:00 perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF The EAX of the CPUID Leaf 023H enumerates the mask of valid sub-leaves. To tell the availability of the sub-leaf 1 (enumerate the counter mask), perf should check the bit 1 (0x2) of EAS, rather than bit 0 (0x1). The error is not user-visible on bare metal. Because the sub-leaf 0 and the sub-leaf 1 are always available. However, it may bring issues in a virtualization environment when a VMM only enumerates the sub-leaf 0. Introduce the cpuid35_e?x to replace the macros, which makes the implementation style consistent. Fixes: eb467aaac21e ("perf/x86/intel: Support Architectural PerfMon Extensi= on leaf") Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20250129154820.3755948-3-kan.liang@linux.in= tel.com --- arch/x86/events/intel/core.c | 18 ++++++++++-------- arch/x86/include/asm/perf_event.h | 28 +++++++++++++++++++++++++--- 2 files changed, 35 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 966f783..f3d5b71 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4905,20 +4905,22 @@ static inline bool intel_pmu_broken_perf_cap(void) =20 static void update_pmu_cap(struct x86_hybrid_pmu *pmu) { - unsigned int sub_bitmaps, eax, ebx, ecx, edx; + unsigned int cntr, fixed_cntr, ecx, edx; + union cpuid35_eax eax; + union cpuid35_ebx ebx; =20 - cpuid(ARCH_PERFMON_EXT_LEAF, &sub_bitmaps, &ebx, &ecx, &edx); + cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx); =20 - if (ebx & ARCH_PERFMON_EXT_UMASK2) + if (ebx.split.umask2) pmu->config_mask |=3D ARCH_PERFMON_EVENTSEL_UMASK2; - if (ebx & ARCH_PERFMON_EXT_EQ) + if (ebx.split.eq) pmu->config_mask |=3D ARCH_PERFMON_EVENTSEL_EQ; =20 - if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { + if (eax.split.cntr_subleaf) { cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, - &eax, &ebx, &ecx, &edx); - pmu->cntr_mask64 =3D eax; - pmu->fixed_cntr_mask64 =3D ebx; + &cntr, &fixed_cntr, &ecx, &edx); + pmu->cntr_mask64 =3D cntr; + pmu->fixed_cntr_mask64 =3D fixed_cntr; } =20 if (!intel_pmu_broken_perf_cap()) { diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 1ac79f3..0ba8d20 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -188,11 +188,33 @@ union cpuid10_edx { * detection/enumeration details: */ #define ARCH_PERFMON_EXT_LEAF 0x00000023 -#define ARCH_PERFMON_EXT_UMASK2 0x1 -#define ARCH_PERFMON_EXT_EQ 0x2 -#define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT 0x1 #define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1 =20 +union cpuid35_eax { + struct { + unsigned int leaf0:1; + /* Counters Sub-Leaf */ + unsigned int cntr_subleaf:1; + /* Auto Counter Reload Sub-Leaf */ + unsigned int acr_subleaf:1; + /* Events Sub-Leaf */ + unsigned int events_subleaf:1; + unsigned int reserved:28; + } split; + unsigned int full; +}; + +union cpuid35_ebx { + struct { + /* UnitMask2 Supported */ + unsigned int umask2:1; + /* EQ-bit Supported */ + unsigned int eq:1; + unsigned int reserved:30; + } split; + unsigned int full; +}; + /* * Intel Architectural LBR CPUID detection/enumeration details: */