From nobody Wed Dec 17 12:45:09 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2727E2046A2; Tue, 10 Dec 2024 18:05:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733853922; cv=none; b=tDl1i3uKB5G9Pgsq3Y8vul3MufvIYx9G7Tv5NBQfXxOYOgg8tFmDCF8lvMkyyQzjzWsQLnNbDXVAP0Xyein1sy586C/G5qrQqhX6KQB8X4WAGKL2yQuFC9DKOoweGseVlwFJAAVRboqospRGSI4FRvLO+pKFFnzMuvER+m8u3tg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733853922; c=relaxed/simple; bh=BieKL7c33cHfp95zpAhOo7VTdJ7dH6kwDaN6DHa5f7A=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=RkyLyhjP6z8WIIn/UFp5vVXb51BuM+PAatnOV04TeXXYUy62gO59u4xKFhj4p5ki4r1m+YdezDAqM545IvGR5vnR+uhibv69n/EnK/mgpVJw7tL5bWYLQZhMIF2iaenXQuf+3iyFrjjlVB+YEcRI43g/CqxRpjNy4ddFqfWOr3o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ChlMB6WF; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=01R9xZ5W; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ChlMB6WF"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="01R9xZ5W" Date: Tue, 10 Dec 2024 18:05:15 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1733853917; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0tDu9FVXJduq6QsDKz+5PkvtmJqYR66/ELZjEogRSyk=; b=ChlMB6WF7I1S5xR4HRoyew+Wbo4I5jbojoFLHIfD5LVN1+K4tYmAPmEJlMbVqMYd2jcR8j 6fsNN6/xX8gBtVZCcBheNjCZkPFjWCtPu7uQb5D0+INTCJKmGi4a8hCXOFZxdxoLLxFb2S hcJGCuZqmHk7N0vx6ljYuko3dQ5M27cj8qTlo7AsXS/88bfcETO3PXj8AjRAbIeo0VjFHh kkwXybzETsmM8miblCt6IlyqKpWnCqhw1C1oNO6kOX6pobs33xNOSjGO3oysUHexOpZlDv ufEFBOeR73jD+jwJFfX3IzYbOCHQIERExY7NA8sImKOvzCd+Yt7a7VTsAcpT6A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1733853917; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0tDu9FVXJduq6QsDKz+5PkvtmJqYR66/ELZjEogRSyk=; b=01R9xZ5WpgAcNLTrB1h1x15fc2m/kFDHxTS1P4/RnMxXSuq6TpZCz5l08Vo/HDyJNDJ213 /uXhZoODJwc51BCA== From: "tip-bot2 for Borislav Petkov (AMD)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cleanups] Documentation: Merge x86-specific boot options doc into kernel-parameters.txt Cc: "Borislav Petkov (AMD)" , Sohil Mehta , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20241202190011.11979-1-bp@kernel.org> References: <20241202190011.11979-1-bp@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <173385391562.412.7209645577276296571.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cleanups branch of tip: Commit-ID: ab0e7f20768af59fe161d71cc5d1de384f2a9da8 Gitweb: https://git.kernel.org/tip/ab0e7f20768af59fe161d71cc5d1de384= f2a9da8 Author: Borislav Petkov (AMD) AuthorDate: Mon, 02 Dec 2024 20:00:10 +01:00 Committer: Borislav Petkov (AMD) CommitterDate: Tue, 10 Dec 2024 18:25:40 +01:00 Documentation: Merge x86-specific boot options doc into kernel-parameters.t= xt Documentation/arch/x86/x86_64/boot-options.rst is causing unnecessary confusion by being a second place where one can put x86 boot options. Move them into the main one. Drop removed ones like "acpi=3Dht", while at it. Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Sohil Mehta Link: https://lore.kernel.org/r/20241202190011.11979-1-bp@kernel.org --- Documentation/admin-guide/kernel-parameters.rst | 3 +- Documentation/admin-guide/kernel-parameters.txt | 237 ++++- Documentation/arch/x86/x86_64/boot-options.rst | 312 +------- Documentation/arch/x86/x86_64/fake-numa-for-cpusets.rst | 2 +- Documentation/arch/x86/x86_64/index.rst | 1 +- arch/x86/Kconfig.debug | 2 +- arch/x86/kernel/pci-dma.c | 4 +- 7 files changed, 227 insertions(+), 334 deletions(-) delete mode 100644 Documentation/arch/x86/x86_64/boot-options.rst diff --git a/Documentation/admin-guide/kernel-parameters.rst b/Documentatio= n/admin-guide/kernel-parameters.rst index 59931f2..39d0e7f 100644 --- a/Documentation/admin-guide/kernel-parameters.rst +++ b/Documentation/admin-guide/kernel-parameters.rst @@ -194,8 +194,6 @@ is applicable:: WDT Watchdog support is enabled. X86-32 X86-32, aka i386 architecture is enabled. X86-64 X86-64 architecture is enabled. - More X86-64 boot options can be found in - Documentation/arch/x86/x86_64/boot-options.rst. X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64) X86_UV SGI UV support is enabled. XEN Xen support is enabled @@ -213,7 +211,6 @@ Do not modify the syntax of boot loader parameters with= out extreme need or coordination with . =20 There are also arch-specific kernel-parameters not documented here. -See for example . =20 Note that ALL kernel parameters listed below are CASE SENSITIVE, and that a trailing =3D on the name of any parameter states that that parameter will diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index dc663c0..bf7b356 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -21,6 +21,10 @@ strictly ACPI specification compliant. rsdt -- prefer RSDT over (default) XSDT copy_dsdt -- copy DSDT to memory + nocmcff -- Disable firmware first mode for corrected + errors. This disables parsing the HEST CMC error + source to check if firmware has set the FF flag. This + may result in duplicate corrected error reports. nospcr -- disable console in ACPI SPCR table as default _serial_ console on ARM64 For ARM64, ONLY "acpi=3Doff", "acpi=3Don", "acpi=3Dforce" or @@ -405,6 +409,8 @@ not play well with APC CPU idle - disable it if you have APC and your system crashes randomly. =20 + apic [APIC,X86-64] Use IO-APIC. Default. + apic=3D [APIC,X86,EARLY] Advanced Programmable Interrupt Controller Change the output verbosity while booting Format: { quiet (default) | verbose | debug } @@ -424,6 +430,10 @@ useful so that a dump capture kernel won't be shot down by NMI =20 + apicpmtimer Do APIC timer calibration using the pmtimer. Implies + apicmaintimer. Useful when your PIT timer is totally + broken. + autoconf=3D [IPV6] See Documentation/networking/ipv6.rst. =20 @@ -1726,6 +1736,8 @@ =20 off: Disable GDS mitigation. =20 + gbpages [X86] Use GB pages for kernel direct mappings. + gcov_persist=3D [GCOV] When non-zero (default), profiling data for kernel modules is saved and remains accessible via debugfs, even when the module is unloaded/reloaded. @@ -2008,12 +2020,21 @@ =20 idle=3D [X86,EARLY] Format: idle=3Dpoll, idle=3Dhalt, idle=3Dnomwait - Poll forces a polling idle loop that can slightly - improve the performance of waking up a idle CPU, but - will use a lot of power and make the system run hot. - Not recommended. + + idle=3Dpoll: Don't do power saving in the idle loop + using HLT, but poll for rescheduling event. This will + make the CPUs eat a lot more power, but may be useful + to get slightly better performance in multiprocessor + benchmarks. It also makes some profiling using + performance counters more accurate. Please note that + on systems with MONITOR/MWAIT support (like Intel + EM64T CPUs) this option has no performance advantage + over the normal idle loop. It may also interact badly + with hyperthreading. + idle=3Dhalt: Halt is forced to be used for CPU idle. In such case C2/C3 won't be used again. + idle=3Dnomwait: Disable mwait for CPU C-states =20 idxd.sva=3D [HW] @@ -2311,20 +2332,73 @@ relaxed =20 iommu=3D [X86,EARLY] + off + Don't initialize and use any kind of IOMMU. + force + Force the use of the hardware IOMMU even when + it is not actually needed (e.g. because < 3 GB + memory). + noforce + Don't force hardware IOMMU usage when it is not + needed. (default). + biomerge panic nopanic merge nomerge + soft - pt [X86] - nopt [X86] - nobypass [PPC/POWERNV] + Use software bounce buffering (SWIOTLB) (default for + Intel machines). This can be used to prevent the usage + of an available hardware IOMMU. + + [X86] + pt + [X86] + nopt + [PPC/POWERNV] + nobypass Disable IOMMU bypass, using IOMMU for PCI devices. =20 + [X86] + AMD Gart HW IOMMU-specific options: + + + Set the size of the remapping area in bytes. + + allowed + Overwrite iommu off workarounds for specific chipsets + + fullflush + Flush IOMMU on each allocation (default). + + nofullflush + Don't use IOMMU fullflush. + + memaper[=3D] + Allocate an own aperture over RAM with size + 32MB< series board detected. + Selecting for reboots." In the case where you + think the quirk is in error (e.g. you have newer BIOS, + or newer board) using this option will ignore the + built-in quirk table, and use the generic default + reboot actions. + + efi + Use efi reset_system runtime service. If EFI is not + configured or the EFI reset does not work, the reboot + path attempts the reset using the keyboard controller. + + force + Don't stop other CPUs on reboot. This can make reboot + more reliable in some cases. + + kbd + Use the keyboard controller. cold reset (default) + + pci + Use a write to the PCI config space register 0xcf9 to + trigger reboot. + + triple + Force a triple fault (init) + + warm + Don't set the cold reboot flag + + Using warm reset will be much faster especially on big + memory systems because the BIOS will not go through + the memory check. Disadvantage is that not all + hardware will be completely reinitialized on reboot so + there may be boot problems on some systems. + + refscale.holdoff=3D [KNL] Set test-start holdoff period. The purpose of this parameter is to delay the start of the @@ -6101,7 +6305,16 @@ =20 serialnumber [BUGS=3DX86-32] =20 - sev=3Doption[,option...] [X86-64] See Documentation/arch/x86/x86_64/boot-= options.rst + sev=3Doption[,option...] [X86-64] + + debug + Enable debug messages. + + nosnp + Do not enable SEV-SNP (applies to host/hypervisor + only). Setting 'nosnp' avoids the RMP check overhead + in memory accesses when users do not want to run + SEV-SNP guests. =20 shapers=3D [NET] Maximal number of shapers. diff --git a/Documentation/arch/x86/x86_64/boot-options.rst b/Documentation= /arch/x86/x86_64/boot-options.rst deleted file mode 100644 index d69e3cf..0000000 --- a/Documentation/arch/x86/x86_64/boot-options.rst +++ /dev/null @@ -1,312 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D -AMD64 Specific Boot Options -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D - -There are many others (usually documented in driver documentation), but -only the AMD64 specific ones are listed here. - -Machine check -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Please see Documentation/arch/x86/x86_64/machinecheck.rst for sysfs runtim= e tunables. - - mce=3Doff - Disable machine check - mce=3Dno_cmci - Disable CMCI(Corrected Machine Check Interrupt) that - Intel processor supports. Usually this disablement is - not recommended, but it might be handy if your hardware - is misbehaving. - Note that you'll get more problems without CMCI than with - due to the shared banks, i.e. you might get duplicated - error logs. - mce=3Ddont_log_ce - Don't make logs for corrected errors. All events reported - as corrected are silently cleared by OS. - This option will be useful if you have no interest in any - of corrected errors. - mce=3Dignore_ce - Disable features for corrected errors, e.g. polling timer - and CMCI. All events reported as corrected are not cleared - by OS and remained in its error banks. - Usually this disablement is not recommended, however if - there is an agent checking/clearing corrected errors - (e.g. BIOS or hardware monitoring applications), conflicting - with OS's error handling, and you cannot deactivate the agent, - then this option will be a help. - mce=3Dno_lmce - Do not opt-in to Local MCE delivery. Use legacy method - to broadcast MCEs. - mce=3Dbootlog - Enable logging of machine checks left over from booting. - Disabled by default on AMD Fam10h and older because some BIOS - leave bogus ones. - If your BIOS doesn't do that it's a good idea to enable though - to make sure you log even machine check events that result - in a reboot. On Intel systems it is enabled by default. - mce=3Dnobootlog - Disable boot machine check logging. - mce=3Dmonarchtimeout (number) - monarchtimeout: - Sets the time in us to wait for other CPUs on machine checks. 0 - to disable. - mce=3Dbios_cmci_threshold - Don't overwrite the bios-set CMCI threshold. This boot option - prevents Linux from overwriting the CMCI threshold set by the - bios. Without this option, Linux always sets the CMCI - threshold to 1. Enabling this may make memory predictive failure - analysis less effective if the bios sets thresholds for memory - errors since we will not see details for all errors. - mce=3Drecovery - Force-enable recoverable machine check code paths - - nomce (for compatibility with i386) - same as mce=3Doff - - Everything else is in sysfs now. - -APICs -=3D=3D=3D=3D=3D - - apic - Use IO-APIC. Default - - noapic - Don't use the IO-APIC. - - disableapic - Don't use the local APIC - - nolapic - Don't use the local APIC (alias for i386 compatibility) - - pirq=3D... - See Documentation/arch/x86/i386/IO-APIC.rst - - noapictimer - Don't set up the APIC timer - - no_timer_check - Don't check the IO-APIC timer. This can work around - problems with incorrect timer initialization on some boards. - - apicpmtimer - Do APIC timer calibration using the pmtimer. Implies - apicmaintimer. Useful when your PIT timer is totally broken. - -Timing -=3D=3D=3D=3D=3D=3D - - notsc - Deprecated, use tsc=3Dunstable instead. - - nohpet - Don't use the HPET timer. - -Idle loop -=3D=3D=3D=3D=3D=3D=3D=3D=3D - - idle=3Dpoll - Don't do power saving in the idle loop using HLT, but poll for resched= uling - event. This will make the CPUs eat a lot more power, but may be useful - to get slightly better performance in multiprocessor benchmarks. It al= so - makes some profiling using performance counters more accurate. - Please note that on systems with MONITOR/MWAIT support (like Intel EM6= 4T - CPUs) this option has no performance advantage over the normal idle lo= op. - It may also interact badly with hyperthreading. - -Rebooting -=3D=3D=3D=3D=3D=3D=3D=3D=3D - - reboot=3Db[ios] | t[riple] | k[bd] | a[cpi] | e[fi] | p[ci] [, [w]arm |= [c]old] - bios - Use the CPU reboot vector for warm reset - warm - Don't set the cold reboot flag - cold - Set the cold reboot flag - triple - Force a triple fault (init) - kbd - Use the keyboard controller. cold reset (default) - acpi - Use the ACPI RESET_REG in the FADT. If ACPI is not configured or - the ACPI reset does not work, the reboot path attempts the reset - using the keyboard controller. - efi - Use efi reset_system runtime service. If EFI is not configured or - the EFI reset does not work, the reboot path attempts the reset us= ing - the keyboard controller. - pci - Use a write to the PCI config space register 0xcf9 to trigger rebo= ot. - - Using warm reset will be much faster especially on big memory - systems because the BIOS will not go through the memory check. - Disadvantage is that not all hardware will be completely reinitialized - on reboot so there may be boot problems on some systems. - - reboot=3Dforce - Don't stop other CPUs on reboot. This can make reboot more reliable - in some cases. - - reboot=3Ddefault - There are some built-in platform specific "quirks" - you may see: - "reboot: series board detected. Selecting for reboots." - In the case where you think the quirk is in error (e.g. you have - newer BIOS, or newer board) using this option will ignore the built-in - quirk table, and use the generic default reboot actions. - -NUMA -=3D=3D=3D=3D - - numa=3Doff - Only set up a single NUMA node spanning all memory. - - numa=3Dnoacpi - Don't parse the SRAT table for NUMA setup - - numa=3Dnohmat - Don't parse the HMAT table for NUMA setup, or soft-reserved memory - partitioning. - -ACPI -=3D=3D=3D=3D - - acpi=3Doff - Don't enable ACPI - acpi=3Dht - Use ACPI boot table parsing, but don't enable ACPI interpreter - acpi=3Dforce - Force ACPI on (currently not needed) - acpi=3Dstrict - Disable out of spec ACPI workarounds. - acpi_sci=3D{edge,level,high,low} - Set up ACPI SCI interrupt. - acpi=3Dnoirq - Don't route interrupts - acpi=3Dnocmcff - Disable firmware first mode for corrected errors. This - disables parsing the HEST CMC error source to check if - firmware has set the FF flag. This may result in - duplicate corrected error reports. - -PCI -=3D=3D=3D - - pci=3Doff - Don't use PCI - pci=3Dconf1 - Use conf1 access. - pci=3Dconf2 - Use conf2 access. - pci=3Drom - Assign ROMs. - pci=3Dassign-busses - Assign busses - pci=3Dirqmask=3DMASK - Set PCI interrupt mask to MASK - pci=3Dlastbus=3DNUMBER - Scan up to NUMBER busses, no matter what the mptable says. - pci=3Dnoacpi - Don't use ACPI to set up PCI interrupt routing. - -IOMMU (input/output memory management unit) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Multiple x86-64 PCI-DMA mapping implementations exist, for example: - - 1. : use no hardware/software IOMMU at all - (e.g. because you have < 3 GB memory). - Kernel boot message: "PCI-DMA: Disabling IOMMU" - - 2. : AMD GART based hardware IOMMU. - Kernel boot message: "PCI-DMA: using GART IOMMU" - - 3. : Software IOMMU implementation. = Used - e.g. if there is no hardware IOMMU in the system and it is need beca= use - you have >3GB memory or told the kernel to us it (iommu=3Dsoft)) - Kernel boot message: "PCI-DMA: Using software bounce buffering - for IO (SWIOTLB)" - -:: - - iommu=3D[][,noagp][,off][,force][,noforce] - [,memaper[=3D]][,merge][,fullflush][,nomerge] - [,noaperture] - -General iommu options: - - off - Don't initialize and use any kind of IOMMU. - noforce - Don't force hardware IOMMU usage when it is not needed. (default). - force - Force the use of the hardware IOMMU even when it is - not actually needed (e.g. because < 3 GB memory). - soft - Use software bounce buffering (SWIOTLB) (default for - Intel machines). This can be used to prevent the usage - of an available hardware IOMMU. - -iommu options only relevant to the AMD GART hardware IOMMU: - - - Set the size of the remapping area in bytes. - allowed - Overwrite iommu off workarounds for specific chipsets. - fullflush - Flush IOMMU on each allocation (default). - nofullflush - Don't use IOMMU fullflush. - memaper[=3D] - Allocate an own aperture over RAM with size 32MB<[,force,noforce] - - Prereserve that many 2K slots for the software IO bounce buffering. - force - Force all IO through the software TLB. - noforce - Do not initialize the software TLB. - - -Miscellaneous -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - - nogbpages - Do not use GB pages for kernel direct mappings. - gbpages - Use GB pages for kernel direct mappings. - - -AMD SEV (Secure Encrypted Virtualization) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Options relating to AMD SEV, specified via the following format: - -:: - - sev=3Doption1[,option2] - -The available options are: - - debug - Enable debug messages. - - nosnp - Do not enable SEV-SNP (applies to host/hypervisor only). Setting - 'nosnp' avoids the RMP check overhead in memory accesses when - users do not want to run SEV-SNP guests. diff --git a/Documentation/arch/x86/x86_64/fake-numa-for-cpusets.rst b/Docu= mentation/arch/x86/x86_64/fake-numa-for-cpusets.rst index ba74617..970ee94 100644 --- a/Documentation/arch/x86/x86_64/fake-numa-for-cpusets.rst +++ b/Documentation/arch/x86/x86_64/fake-numa-for-cpusets.rst @@ -18,7 +18,7 @@ For more information on the features of cpusets, see Documentation/admin-guide/cgroup-v1/cpusets.rst. There are a number of different configurations you can use for your needs.= For more information on the numa=3Dfake command line option and its various wa= ys of -configuring fake nodes, see Documentation/arch/x86/x86_64/boot-options.rst. +configuring fake nodes, see Documentation/admin-guide/kernel-parameters.txt =20 For the purposes of this introduction, we'll assume a very primitive NUMA emulation setup of "numa=3Dfake=3D4*512,". This will split our system mem= ory into diff --git a/Documentation/arch/x86/x86_64/index.rst b/Documentation/arch/x= 86/x86_64/index.rst index ad15e9b..a026195 100644 --- a/Documentation/arch/x86/x86_64/index.rst +++ b/Documentation/arch/x86/x86_64/index.rst @@ -7,7 +7,6 @@ x86_64 Support .. toctree:: :maxdepth: 2 =20 - boot-options uefi mm 5level-paging diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 74777a9..1eb4d23 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -97,7 +97,7 @@ config IOMMU_DEBUG code. When you use it make sure you have a big enough IOMMU/AGP aperture. Most of the options enabled by this can be set more finegrained using the iommu=3D command line - options. See Documentation/arch/x86/x86_64/boot-options.rst for more + options. See Documentation/admin-guide/kernel-parameters.txt for more details. =20 config IOMMU_LEAK diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index f323d83..6267363 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -108,10 +108,6 @@ void __init pci_iommu_alloc(void) swiotlb_init(x86_swiotlb_enable, x86_swiotlb_flags); } =20 -/* - * See for the iommu kern= el - * parameter documentation. - */ static __init int iommu_setup(char *p) { iommu_merge =3D 1;