From nobody Thu Dec 18 20:07:03 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 243D618E02A; Wed, 4 Dec 2024 20:39:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733344787; cv=none; b=kF1/So9JMDGhVpBH5mn2dBfZ0eL9ukOEN9mCI2VnWyh2LCn0OIoeKXUMVNJejblokKUfvrsprYwkc61Dyd1EqWS6JkVk6MyEohgg5gdLnT0ayZTuyirKe9fuXqix8q549l90jsw53WrLcAcTM8O8KVqVEJMS8TrTtdkNV8QtXiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733344787; c=relaxed/simple; bh=9buZEb2X77sNHuyBwseJrXQxsmZbvUjrIxGCs1RNYBU=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=s2FlboWeKuPmMWLmo787CodRhdo7DMVwMTpOn52tFbU3f63E1sLMXCshZz46Qgq2bCCaeP+HFUIqK7j+5XESAmHqNFMe7NNymIVKerD9e2XZxBh+4tBE5Yjfgg3sWxfqbnQACn4r7jQycRcWC1Jiy2b+U1wVQpyB0aBej1vxoxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=W7903zJh; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=u9Q8s5ab; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="W7903zJh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="u9Q8s5ab" Date: Wed, 04 Dec 2024 20:39:43 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1733344784; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Yid1eSqSo8HI1ZkY8JaBTagIek04H3U6SC4TXGkhz0I=; b=W7903zJhQthmcpD6UuAZu77PRjbP6W8SwmpgPAILhPnKqU5Uw7BS5Bos8zFC6lauDXKVH1 TWC//+Q7eQrrrBZrHXGq4oT6m4M0lAlO/CTfgbuJ0+nH3KdYcQ18uvwCzTBuZauug528kQ W1qm9IGDOMHocUFpYJH1zzOhBsZYc9HE059lM+qMzuYo/SVi3lZgZp0/oLQX46dNr/4wjW iktBJAV8zl2uxls9KIfamf5kbFMJ1Z4edBf0WAmXFcYAlocfn5vKv2FMthhFedt8KSLKgd ExrVKGaWz3/Oq3UYUMvLJ/fDg3sApuFgPonVVIZ2BGeU6f247W9spj+cY59r8g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1733344784; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=Yid1eSqSo8HI1ZkY8JaBTagIek04H3U6SC4TXGkhz0I=; b=u9Q8s5abwNQ2qYsScTaIoQ2yr5RgI32XePhZKy79adZlxzP17wEqQ/gNtdPuSW3mKYlbVn o65zycqhVS6TrpDQ== From: "tip-bot2 for Sohil Mehta" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/cpufeatures: Free up unused feature bits Cc: Sohil Mehta , Dave Hansen , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <173334478346.412.3186447152849006342.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: a734d9d653faf3ddfbe09ef30f31e8977418515c Gitweb: https://git.kernel.org/tip/a734d9d653faf3ddfbe09ef30f31e8977= 418515c Author: Sohil Mehta AuthorDate: Thu, 07 Nov 2024 23:30:00=20 Committer: Dave Hansen CommitterDate: Wed, 04 Dec 2024 12:27:13 -08:00 x86/cpufeatures: Free up unused feature bits Linux defined feature bits X86_FEATURE_P3 and X86_FEATURE_P4 are not used anywhere. Commit f31d731e4467 ("x86: use X86_FEATURE_NOPL in alternatives") got rid of the last usage in 2008. Remove the related mappings and code. Just like all X86_FEATURE bits, the raw bit numbers can be exposed to userspace via MODULE_DEVICE_TABLE(). There is a very small theoretical chance of userspace getting confused if these bits got reassigned and changed logical meaning. But these bits were never used for a device table, so it's highly unlikely this will ever happen in practice. [ dhansen: clarify userspace visibility of these bits ] Signed-off-by: Sohil Mehta Signed-off-by: Dave Hansen Acked-by: Dave Hansen Link: https://lore.kernel.org/all/20241107233000.2742619-1-sohil.mehta%40in= tel.com --- arch/x86/include/asm/cpufeatures.h | 4 ++-- arch/x86/kernel/cpu/intel.c | 5 ----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 05e985c..de3f299 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -83,8 +83,8 @@ #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* "centaur_mcr" Centaur MCRs = (=3D MTRRs) */ #define X86_FEATURE_K8 ( 3*32+ 4) /* Opteron, Athlon64 */ #define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitectur= e */ -#define X86_FEATURE_P3 ( 3*32+ 6) /* P3 */ -#define X86_FEATURE_P4 ( 3*32+ 7) /* P4 */ +/* Free ( 3*32+ 6) */ +/* Free ( 3*32+ 7) */ #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* "constant_tsc" TSC ticks at= a constant rate */ #define X86_FEATURE_UP ( 3*32+ 9) /* "up" SMP kernel running on UP */ #define X86_FEATURE_ART ( 3*32+10) /* "art" Always running timer (ART) */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index e7656cb..1c892eb 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -628,11 +628,6 @@ static void init_intel(struct cpuinfo_x86 *c) if (p) strcpy(c->x86_model_id, p); } - - if (c->x86 =3D=3D 15) - set_cpu_cap(c, X86_FEATURE_P4); - if (c->x86 =3D=3D 6) - set_cpu_cap(c, X86_FEATURE_P3); #endif =20 /* Work around errata */