From nobody Sun Nov 24 07:01:30 2024 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B75320E031; Wed, 6 Nov 2024 23:32:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730935958; cv=none; b=aK2dIUGSJUPLdBQThLCUIZTXRJK2fAFm3yfHFEP2BDJ8TuWwXW6PeWa9LvySja+/0fQWhXPRclYLXc5iqTBUbhE05kzGnkLQwwcSPL8yuwnjPJw6+SUHOgzudIQ4gSNVB+Nc15zMNORlEpZtlqtX7Dkej/gxyhjoqIJcU4HaXV8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730935958; c=relaxed/simple; bh=xu57MnpZb9w96iBTN0MxBbBFWTuwNqLI2CWkftWkpIc=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=IQTEbDNKF3CykoOze7nCA0103HjgOnaPeEEfOkIb0Sn1iu1QXmQsbXAfODYyEMFrCTxS1tvhIozgsg+QO2kRkc3Ib8K8ayuglC47B8Mhe86qzBxeKUhCuxiWl9uygU3kDZSg4JCzNoG/6o02jJFDAEZBMJ3EPnMFlRG2WA8+HZs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=StoCZu8f; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=7qjORmVv; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="StoCZu8f"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="7qjORmVv" Date: Wed, 06 Nov 2024 23:32:33 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1730935954; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OokbEherWyjjgEsj4f6IZQhzN170HqlXnGSi9TAH/0s=; b=StoCZu8fhNI+Ca6s8ZRQCCD81bZ8mEMjRuKfY6MoFrjjc4iUuvR+sJGwGJIC4Y2pR+5DrV 3c882llDwu7d1XFPlO9dE5MYOsZrGAtpUaDuqHz8PqjnXat61cpZOVv6SZ+Dulsm6lZfL9 6/XBfpzyfGW7qEuXBfeIGQbAVqrAbmVZQ7vaoXYmPkQvSBhlYUfBUlA1FAuytPOdOv9L/E g7ybpQAEl1o8NKZGHNclupNblovkaiOCwNBsunifbRlzY5pjdPN0LBPm1G0Sbp9Olpm4oe LETdV07IoX6OeyF7Enn30nWKV68JVcDWCnyqob3CJigjK9dvOrKQk2b+7qoEAg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1730935954; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OokbEherWyjjgEsj4f6IZQhzN170HqlXnGSi9TAH/0s=; b=7qjORmVv49vblAuzt7a7hPFqzku/TvIlo+nkJbxuzt0X6HLyKsNnCSdkXHB8RxngigdU5b aBzsVoFkMo96HwCQ== From: "tip-bot2 for Inochi Amaoto" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] irqchip: Add T-HEAD C900 ACLINT SSWI driver Cc: Inochi Amaoto , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20241031060859.722258-3-inochiama@gmail.com> References: <20241031060859.722258-3-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <173093595337.32228.8989558114894431765.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/core branch of tip: Commit-ID: 25caea955cc950507d179f3ef456404b475e8c23 Gitweb: https://git.kernel.org/tip/25caea955cc950507d179f3ef456404b4= 75e8c23 Author: Inochi Amaoto AuthorDate: Thu, 31 Oct 2024 14:08:58 +08:00 Committer: Thomas Gleixner CommitterDate: Thu, 07 Nov 2024 00:28:27 +01:00 irqchip: Add T-HEAD C900 ACLINT SSWI driver Add a driver for the T-HEAD C900 ACLINT SSWI device. This device allows the system with T-HEAD cpus to send ipi via fast device interface. Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20241031060859.722258-3-inochiama@gmail.c= om --- drivers/irqchip/Kconfig | 12 +- drivers/irqchip/Makefile | 1 +- drivers/irqchip/irq-thead-c900-aclint-sswi.c | 176 ++++++++++++++++++- include/linux/cpuhotplug.h | 1 +- 4 files changed, 190 insertions(+) create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index ef0fa69..9cac136 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -619,6 +619,18 @@ config STARFIVE_JH8100_INTC =20 If you don't know what to do here, say Y. =20 +config THEAD_C900_ACLINT_SSWI + bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" + depends on RISCV + depends on SMP + select IRQ_DOMAIN_HIERARCHY + select GENERIC_IRQ_IPI_MUX + help + This enables support for T-HEAD specific ACLINT SSWI device + support. + + If you don't know what to do here, say Y. + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 15ed6e9..25e9ad2 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi= .o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_STARFIVE_JH8100_INTC) +=3D irq-starfive-jh8100-intc.o +obj-$(CONFIG_THEAD_C900_ACLINT_SSWI) +=3D irq-thead-c900-aclint-sswi.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o obj-$(CONFIG_IMX_MU_MSI) +=3D irq-imx-mu-msi.o diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip= /irq-thead-c900-aclint-sswi.c new file mode 100644 index 0000000..b0e366a --- /dev/null +++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Inochi Amaoto + */ + +#define pr_fmt(fmt) "thead-c900-aclint-sswi: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define THEAD_ACLINT_xSWI_REGISTER_SIZE 4 + +#define THEAD_C9XX_CSR_SXSTATUS 0x5c0 +#define THEAD_C9XX_SXSTATUS_CLINTEE BIT(17) + +static int sswi_ipi_virq __ro_after_init; +static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs); + +static void thead_aclint_sswi_ipi_send(unsigned int cpu) +{ + writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu)); +} + +static void thead_aclint_sswi_ipi_clear(void) +{ + writel_relaxed(0x0, this_cpu_read(sswi_cpu_regs)); +} + +static void thead_aclint_sswi_ipi_handle(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + + csr_clear(CSR_IP, IE_SIE); + thead_aclint_sswi_ipi_clear(); + + ipi_mux_process(); + + chained_irq_exit(chip, desc); +} + +static int thead_aclint_sswi_starting_cpu(unsigned int cpu) +{ + enable_percpu_irq(sswi_ipi_virq, irq_get_trigger_type(sswi_ipi_virq)); + + return 0; +} + +static int thead_aclint_sswi_dying_cpu(unsigned int cpu) +{ + thead_aclint_sswi_ipi_clear(); + + disable_percpu_irq(sswi_ipi_virq); + + return 0; +} + +static int __init thead_aclint_sswi_parse_irq(struct fwnode_handle *fwnode, + void __iomem *reg) +{ + struct of_phandle_args parent; + unsigned long hartid; + u32 contexts, i; + int rc, cpu; + + contexts =3D of_irq_count(to_of_node(fwnode)); + if (!(contexts)) { + pr_err("%pfwP: no ACLINT SSWI context available\n", fwnode); + return -EINVAL; + } + + for (i =3D 0; i < contexts; i++) { + rc =3D of_irq_parse_one(to_of_node(fwnode), i, &parent); + if (rc) + return rc; + + rc =3D riscv_of_parent_hartid(parent.np, &hartid); + if (rc) + return rc; + + if (parent.args[0] !=3D RV_IRQ_SOFT) + return -ENOTSUPP; + + cpu =3D riscv_hartid_to_cpuid(hartid); + + per_cpu(sswi_cpu_regs, cpu) =3D reg + i * THEAD_ACLINT_xSWI_REGISTER_SIZ= E; + } + + pr_info("%pfwP: register %u CPU%s\n", fwnode, contexts, str_plural(contex= ts)); + + return 0; +} + +static int __init thead_aclint_sswi_probe(struct fwnode_handle *fwnode) +{ + struct irq_domain *domain; + void __iomem *reg; + int virq, rc; + + /* If it is T-HEAD CPU, check whether SSWI is enabled */ + if (riscv_cached_mvendorid(0) =3D=3D THEAD_VENDOR_ID && + !(csr_read(THEAD_C9XX_CSR_SXSTATUS) & THEAD_C9XX_SXSTATUS_CLINTEE)) + return -ENOTSUPP; + + if (!is_of_node(fwnode)) + return -EINVAL; + + reg =3D of_iomap(to_of_node(fwnode), 0); + if (!reg) + return -ENOMEM; + + /* Parse SSWI setting */ + rc =3D thead_aclint_sswi_parse_irq(fwnode, reg); + if (rc < 0) + return rc; + + /* If mulitple SSWI devices are present, do not register irq again */ + if (sswi_ipi_virq) + return 0; + + /* Find riscv intc domain and create IPI irq mapping */ + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_A= NY); + if (!domain) { + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); + return -ENOENT; + } + + sswi_ipi_virq =3D irq_create_mapping(domain, RV_IRQ_SOFT); + if (!sswi_ipi_virq) { + pr_err("unable to create ACLINT SSWI IRQ mapping\n"); + return -ENOMEM; + } + + /* Register SSWI irq and handler */ + virq =3D ipi_mux_create(BITS_PER_BYTE, thead_aclint_sswi_ipi_send); + if (virq <=3D 0) { + pr_err("unable to create muxed IPIs\n"); + irq_dispose_mapping(sswi_ipi_virq); + return virq < 0 ? virq : -ENOMEM; + } + + irq_set_chained_handler(sswi_ipi_virq, thead_aclint_sswi_ipi_handle); + + cpuhp_setup_state(CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING, + "irqchip/thead-aclint-sswi:starting", + thead_aclint_sswi_starting_cpu, + thead_aclint_sswi_dying_cpu); + + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + + /* Announce that SSWI is providing IPIs */ + pr_info("providing IPIs using THEAD ACLINT SSWI\n"); + + return 0; +} + +static int __init thead_aclint_sswi_early_probe(struct device_node *node, + struct device_node *parent) +{ + return thead_aclint_sswi_probe(&node->fwnode); +} +IRQCHIP_DECLARE(thead_aclint_sswi, "thead,c900-aclint-sswi", thead_aclint_= sswi_early_probe); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 2361ed4..7990522 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -147,6 +147,7 @@ enum cpuhp_state { CPUHP_AP_IRQ_EIOINTC_STARTING, CPUHP_AP_IRQ_AVECINTC_STARTING, CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING, CPUHP_AP_IRQ_RISCV_IMSIC_STARTING, CPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING, CPUHP_AP_ARM_MVEBU_COHERENCY,