From nobody Wed Nov 27 02:29:00 2024 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C34AA1E1C33; Tue, 15 Oct 2024 08:57:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728982656; cv=none; b=m4qCTrjD+Fp+weYapvSkgq9xuhUwiscYtCd1rXPYpsx97vtk26tQhceoGqcR1qvyMZRa7iKgmH0tTVjND3kY/7hMQa/PRyohnitJa73TdESERbax0ne/ur/f5wlOdXyf/dAz2oXbEwQX1BDPETo+9+6oc9V6deMvo8vHLjQFDLw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728982656; c=relaxed/simple; bh=1KKT/3hDWE/pMKefjVLfRnlkqADP59e6Zh9BMA5clTs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=KxZ7nbDdowbOumK28xjG7P6QD4jwPAKH0C6nNmK3oviOJ7QIUK9xwUNMu2fSXYbA95I51kAWg0AdSwGVY747HiVrgpCCG7AAKejKVXJq0NplUlWiVH0QTNgeP9RacGvRqdS2Bdu0/GuwGPyK4ePTMbypapoN76Mb48GZLlOz50w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 51D08201E88; Tue, 15 Oct 2024 10:57:32 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id D9AED200C87; Tue, 15 Oct 2024 10:57:31 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id B73B9183DC02; Tue, 15 Oct 2024 16:57:29 +0800 (+08) From: Richard Zhu To: kw@linux.com, manivannan.sadhasivam@linaro.org, bhelgaas@google.com, lpieralisi@kernel.org, frank.li@nxp.com, l.stach@pengutronix.de, robh+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, krzysztof.kozlowski+dt@linaro.org, festevam@gmail.com, s.hauer@pengutronix.de Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v4 6/9] PCI: imx6: Make *_enable_ref_clk() function symmetric Date: Tue, 15 Oct 2024 16:33:30 +0800 Message-Id: <1728981213-8771-7-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1728981213-8771-1-git-send-email-hongxing.zhu@nxp.com> References: <1728981213-8771-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Ensure the *_enable_ref_clk() function is symmetric by addressing missing disable parts on some platforms. Also, remove the duplicate imx7d_pcie_init_phy() function as it is the same as imx7d_pcie_enable_ref_clk(). Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 33 +++++++++++---------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 93e2bcf9aa0a..161daad34a94 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -388,13 +388,6 @@ static int imx8mq_pcie_init_phy(struct imx_pcie *imx_p= cie) return 0; } =20 -static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie) -{ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_P= HY_REFCLK_SEL, 0); - - return 0; -} - static int imx_pcie_init_phy(struct imx_pcie *imx_pcie) { regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -593,13 +586,13 @@ static int imx_pcie_attach_pd(struct device *dev) =20 static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enab= le) { - if (enable) - regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); return 0; } =20 + static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enabl= e) { if (enable) { @@ -625,19 +618,20 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie= *imx_pcie, bool enable) { int offset =3D imx_pcie_grp_offset(imx_pcie); =20 - if (enable) { - regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_= OVERRIDE); - regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OV= ERRIDE_EN); - } - + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); return 0; } =20 static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enabl= e) { - if (!enable) - regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); return 0; } =20 @@ -1522,7 +1516,6 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .clks_cnt =3D ARRAY_SIZE(imx6q_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, - .init_phy =3D imx7d_pcie_init_phy, .enable_ref_clk =3D imx7d_pcie_enable_ref_clk, .core_reset =3D imx7d_pcie_core_reset, }, --=20 2.37.1