From nobody Wed Nov 27 04:46:51 2024 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0534E4C7E; Mon, 14 Oct 2024 06:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728885725; cv=none; b=KyRkis10e0FMlL0TlSnCWe0gyVn3Plzulb3MuQSNyruzyCd7LYJDCBkEXBSpCCdKs7zlLccfInd7wjST1fvJpdBve9jFFGWW/DftX/pm/0y6RDleI+x0FEzChU8ntCwH5+nnU7AwAjPD/2AehKbNN442rvI958CLOO6xwRdxetQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728885725; c=relaxed/simple; bh=zkIqdZum/IGaRw9kiHLzNgVY56MJxqryiegzsUheLfE=; h=From:To:Subject:Date:Message-Id; b=NEfQNCY6YxIXJICE3igWzZMFz5LXVbWGj95nnMV3wncLa1SHQEdTn7OrR3aIrHVsrAKrBGcvExvIeJ7tzfI7BHBuEj6azcK9kQ49dve3+ceUHFmowko6ELLlKwsNm/HQwMyhpNFv5sTWZe2KBPEjXd4IaVl/1AHyjxhm+kDCzJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 590D51A1440; Mon, 14 Oct 2024 08:02:02 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1F2501A1281; Mon, 14 Oct 2024 08:02:02 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 906AF183DC03; Mon, 14 Oct 2024 14:02:00 +0800 (+08) From: Shengjiu Wang To: shengjiu.wang@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, nicoleotsuka@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, linuxppc-dev@lists.ozlabs.org, linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] ASoC: fsl_micfil: Add sample rate constraint Date: Mon, 14 Oct 2024 13:38:33 +0800 Message-Id: <1728884313-6778-1-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On some platforms, for example i.MX93, there is only one audio PLL source, so some sample rate can't be supported. If the PLL source is used for 8kHz series rates, then 11kHz series rates can't be supported. So add constraints according to the frequency of available clock sources, then alsa-lib will help to convert the unsupported rate for the driver. Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_micfil.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c index 4e65966d54fc..619ee7a5b867 100644 --- a/sound/soc/fsl/fsl_micfil.c +++ b/sound/soc/fsl/fsl_micfil.c @@ -28,6 +28,13 @@ =20 #define MICFIL_OSR_DEFAULT 16 =20 +#define MICFIL_NUM_RATES 7 +#define MICFIL_CLK_SRC_NUM 3 +/* clock source ids */ +#define MICFIL_AUDIO_PLL1 0 +#define MICFIL_AUDIO_PLL2 1 +#define MICFIL_CLK_EXT3 2 + enum quality { QUALITY_HIGH, QUALITY_MEDIUM, @@ -45,9 +52,12 @@ struct fsl_micfil { struct clk *mclk; struct clk *pll8k_clk; struct clk *pll11k_clk; + struct clk *clk_src[MICFIL_CLK_SRC_NUM]; struct snd_dmaengine_dai_dma_data dma_params_rx; struct sdma_peripheral_config sdmacfg; struct snd_soc_card *card; + struct snd_pcm_hw_constraint_list constraint_rates; + unsigned int constraint_rates_list[MICFIL_NUM_RATES]; unsigned int dataline; char name[32]; int irq[MICFIL_IRQ_LINES]; @@ -450,12 +460,34 @@ static int fsl_micfil_startup(struct snd_pcm_substrea= m *substream, struct snd_soc_dai *dai) { struct fsl_micfil *micfil =3D snd_soc_dai_get_drvdata(dai); + unsigned int rates[MICFIL_NUM_RATES] =3D {8000, 11025, 16000, 22050, 3200= 0, 44100, 48000}; + int i, j, k =3D 0; + u64 clk_rate; =20 if (!micfil) { dev_err(dai->dev, "micfil dai priv_data not set\n"); return -EINVAL; } =20 + micfil->constraint_rates.list =3D micfil->constraint_rates_list; + micfil->constraint_rates.count =3D 0; + + for (j =3D 0; j < MICFIL_NUM_RATES; j++) { + for (i =3D 0; i < MICFIL_CLK_SRC_NUM; i++) { + clk_rate =3D clk_get_rate(micfil->clk_src[i]); + if (clk_rate !=3D 0 && do_div(clk_rate, rates[j]) =3D=3D 0) { + micfil->constraint_rates_list[k++] =3D rates[j]; + micfil->constraint_rates.count++; + break; + } + } + } + + if (micfil->constraint_rates.count > 0) + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &micfil->constraint_rates); + return 0; } =20 @@ -1160,6 +1192,12 @@ static int fsl_micfil_probe(struct platform_device *= pdev) fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk, &micfil->pll11k_clk); =20 + micfil->clk_src[MICFIL_AUDIO_PLL1] =3D micfil->pll8k_clk; + micfil->clk_src[MICFIL_AUDIO_PLL2] =3D micfil->pll11k_clk; + micfil->clk_src[MICFIL_CLK_EXT3] =3D devm_clk_get(&pdev->dev, "clkext3"); + if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3])) + micfil->clk_src[MICFIL_CLK_EXT3] =3D NULL; + /* init regmap */ regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(regs)) --=20 2.34.1