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McKenney" , Breno Leitao , "Peter Zijlstra (Intel)" , Sandipan Das , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20241001141020.2620361-1-leitao@debian.org> References: <20241001141020.2620361-1-leitao@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <172838550950.1442.11370441097683144204.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: de20037e1b3c2f2ca97b8c12b8c7bca8abd509a7 Gitweb: https://git.kernel.org/tip/de20037e1b3c2f2ca97b8c12b8c7bca8a= bd509a7 Author: Breno Leitao AuthorDate: Tue, 01 Oct 2024 07:10:19 -07:00 Committer: Peter Zijlstra CommitterDate: Mon, 07 Oct 2024 09:28:46 +02:00 perf/x86/amd: Warn only on new bits set Warning at every leaking bits can cause a flood of message, triggering various stall-warning mechanisms to fire, including CSD locks, which makes the machine to be unusable. Track the bits that are being leaked, and only warn when a new bit is set. That said, this patch will help with the following issues: 1) It will tell us which bits are being set, so, it is easy to communicate it back to vendor, and to do a root-cause analyzes. 2) It avoid the machine to be unusable, because, worst case scenario, the user gets less than 60 WARNs (one per unhandled bit). Suggested-by: Paul E. McKenney Signed-off-by: Breno Leitao Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Sandipan Das Reviewed-by: Paul E. McKenney Link: https://lkml.kernel.org/r/20241001141020.2620361-1-leitao@debian.org --- arch/x86/events/amd/core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 920e3a6..b4a1a25 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -943,11 +943,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct pe= rf_branch_entry *entries, u static int amd_pmu_v2_handle_irq(struct pt_regs *regs) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); + static atomic64_t status_warned =3D ATOMIC64_INIT(0); + u64 reserved, status, mask, new_bits, prev_bits; struct perf_sample_data data; struct hw_perf_event *hwc; struct perf_event *event; int handled =3D 0, idx; - u64 reserved, status, mask; bool pmu_enabled; =20 /* @@ -1012,7 +1013,12 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *reg= s) * the corresponding PMCs are expected to be inactive according to the * active_mask */ - WARN_ON(status > 0); + if (status > 0) { + prev_bits =3D atomic64_fetch_or(status, &status_warned); + // A new bit was set for the very first time. + new_bits =3D status & ~prev_bits; + WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits); + } =20 /* Clear overflow and freeze bits */ amd_pmu_ack_global_status(~status);