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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D8.mail.protection.outlook.com (10.167.241.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Mon, 7 Oct 2024 15:06:26 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 7 Oct 2024 10:06:24 -0500 Received: from xhdradheys41.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Mon, 7 Oct 2024 10:06:20 -0500 From: Radhey Shyam Pandey To: , , , , , , , , CC: , , , , , Abin Joseph , Radhey Shyam Pandey Subject: [PATCH net-next v2 1/3] dt-bindings: net: emaclite: Add clock support Date: Mon, 7 Oct 2024 20:36:01 +0530 Message-ID: <1728313563-722267-2-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1728313563-722267-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1728313563-722267-1-git-send-email-radhey.shyam.pandey@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: radhey.shyam.pandey@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|DM4PR12MB5841:EE_ X-MS-Office365-Filtering-Correlation-Id: 08ddaa96-7aa7-4ec6-9a4a-08dce6e19d8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 15:06:26.3382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08ddaa96-7aa7-4ec6-9a4a-08dce6e19d8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5841 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Abin Joseph Add s_axi_aclk AXI4 clock support. Traditionally this IP was used on microblaze platforms which had fixed clocks enabled all the time. But since its a PL IP, it can also be used on SoC platforms like Zynq UltraScale+ MPSoC which combines processing system (PS) and user programmable logic (PL) into the same device. On these platforms instead of fixed enabled clocks it is mandatory to explicitly enable IP clocks for proper functionality. So make clock a required property and also define max supported clock constraints. Signed-off-by: Abin Joseph Signed-off-by: Radhey Shyam Pandey Acked-by: Conor Dooley --- Changes for v2: - Describe clocks as required property. --- Documentation/devicetree/bindings/net/xlnx,emaclite.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml b/Doc= umentation/devicetree/bindings/net/xlnx,emaclite.yaml index 92d8ade988f6..e16384aff557 100644 --- a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml @@ -29,6 +29,9 @@ properties: interrupts: maxItems: 1 =20 + clocks: + maxItems: 1 + phy-handle: true =20 local-mac-address: true @@ -45,6 +48,7 @@ required: - compatible - reg - interrupts + - clocks - phy-handle =20 additionalProperties: false @@ -56,6 +60,7 @@ examples: reg =3D <0x40e00000 0x10000>; interrupt-parent =3D <&axi_intc_1>; interrupts =3D <1>; + clocks =3D <&dummy>; local-mac-address =3D [00 00 00 00 00 00]; phy-handle =3D <&phy0>; xlnx,rx-ping-pong; --=20 2.34.1