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Mon, 30 Sep 2024 14:55:58 -0500 From: Radhey Shyam Pandey To: , , , , , , , , , , , , CC: , , , , Subject: [PATCH net-next 3/3] net: emaclite: Adopt clock support Date: Tue, 1 Oct 2024 01:25:38 +0530 Message-ID: <1727726138-2203615-4-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1727726138-2203615-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1727726138-2203615-1-git-send-email-radhey.shyam.pandey@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0002256F:EE_|CY8PR12MB7706:EE_ X-MS-Office365-Filtering-Correlation-Id: a4d10f1e-cc93-4f43-e60f-08dce189eac4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?N9y6P7ZH164ktDgeAKd79yr7n8KZNrSnlaLCl5HhhFL+ckQVPnCBULPuUPBW?= =?us-ascii?Q?OckRqieO/tOL8mRLhv6yfIcC+ECV15A7g2w+fGkUJ5KNBlQjuecJVHqbo6gr?= =?us-ascii?Q?fuqASCDDd/hu79iMngfbUgYtfRFSGvVabHx93K9N3QepgUOrRUr7ZlB4m0lx?= =?us-ascii?Q?pfz2xLdakBljOXY/rT2BkJ5tMvXjaBsmWVJAU01JJVTh8poZJ5QFtgtnBCOr?= =?us-ascii?Q?6LB+rl5uHvk/AenG7Vl8hzcGjy8vxJM9f2O0xfVvCf24s9rJ5Z+w1sfLrpKu?= =?us-ascii?Q?A9bWnRcPj079GtwybW0g3dwtXrSReojRlNnIyjai4/0v/yksiuDvNc6dcxQa?= =?us-ascii?Q?rKmJCxhjs5Jif8XkiK5agsVKdHPKEuNOKjx7v+WAx0vWpuYZEpD6VGaVDmFz?= =?us-ascii?Q?Ck96eB39Z/XMjQ8TofG4cLYL6v9x32EjVTSS9tsnOuIb8vG1QsOxiCYsdY1I?= =?us-ascii?Q?eLwj7p02uMR31fHN1lhMFDHwfzSXVh9hjjrKLmJbs7wmJn6hUBMzshJ32+cZ?= =?us-ascii?Q?nfLrpnojM7cU/Zt5PpwQBe5IamirJyNohh//I0WxNEGwFOsAXVbege7ARQZx?= =?us-ascii?Q?/91bCeClV7YeruXQW9Eln+K64jVzftNeXs9806hmdSpRek5d5K4/7aJAl71f?= =?us-ascii?Q?FcyAbEZH18CHaH6GPPFlPOaUEOK/lHNYss96oceC6Rj5otenhsIHo+zAWUh7?= =?us-ascii?Q?OBnba0naVHBSipkT0zBUTINQcEdpHPk1+i7xbnPC5AqBLw9AMo/Wi5vsQfqc?= =?us-ascii?Q?jsuDE3oW0gPxdJ7Dv1YkkCafMPetz1t37XcGdqK09hdmeWSlkJBzaJ+ODfix?= =?us-ascii?Q?flmb0ya/3ausB8R38nz/+vJAdfTD8JOTYf8owIEYTmLAvo0vja7Lp7S1uER8?= =?us-ascii?Q?njA/Ez+6tkJ7vX4QgaqinnROlnDZMtQlOAcylvpCHD4Kj/QkWHmeN16tGDFk?= =?us-ascii?Q?3axYDlLiG1sr0wdbIpMezDEs9A3Wf4yoLa65BqF9+HHDUs7zFQzHPI3vdo+K?= =?us-ascii?Q?yzU1tF+vnHUrKD0uwtMCB8OANA+GKE+vfu6FoAdTzom1gHKrN72Rl6maLxJx?= =?us-ascii?Q?aKA7A8jL3rXOaC/D3no9EepM7TjR6UYgMSa6Qx5WxpOwtChF/T2mdsJQ8Rq5?= =?us-ascii?Q?2THK6sH84eqCvEXeynFMkrRR65t3+SSIeaFM+eYmp1YWarMk9yhEjR46x0yW?= =?us-ascii?Q?tHz0Pfp95niDExPYEsf7UupWAOVCtk1t8qwRO0p4LlV6y3iOB5+Q3h0zA2sh?= =?us-ascii?Q?dlM5HMXQj5wRRChqPqwPbO3dVpBV9xjv8CCUw1J33pfgAMZ61HCBv6JlzbDr?= =?us-ascii?Q?6XmuzHHFulEToxHXm/Px6N1RXRQHKyTZETB5ecO2Az6LAISOYn5gSTK/DZNT?= =?us-ascii?Q?cgp5qK9MVjFzEenO0wIsnJ//ty7B?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2024 19:56:04.4684 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4d10f1e-cc93-4f43-e60f-08dce189eac4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7706 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Abin Joseph Adapt to use the clock framework. Add s_axi_aclk clock from the processor bus clock domain and make clk optional to keep DTB backward compatibility. Signed-off-by: Abin Joseph Signed-off-by: Radhey Shyam Pandey --- drivers/net/ethernet/xilinx/xilinx_emaclite.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/et= hernet/xilinx/xilinx_emaclite.c index 13ac619df273..4f469eaffa07 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -7,6 +7,7 @@ * Copyright (c) 2007 - 2013 Xilinx, Inc. */ =20 +#include #include #include #include @@ -1091,6 +1092,7 @@ static int xemaclite_of_probe(struct platform_device = *ofdev) struct net_device *ndev =3D NULL; struct net_local *lp =3D NULL; struct device *dev =3D &ofdev->dev; + struct clk *clkin; =20 int rc =3D 0; =20 @@ -1127,6 +1129,12 @@ static int xemaclite_of_probe(struct platform_device= *ofdev) lp->tx_ping_pong =3D get_bool(ofdev, "xlnx,tx-ping-pong"); lp->rx_ping_pong =3D get_bool(ofdev, "xlnx,rx-ping-pong"); =20 + clkin =3D devm_clk_get_optional_enabled(&ofdev->dev, NULL); + if (IS_ERR(clkin)) { + return dev_err_probe(&ofdev->dev, PTR_ERR(clkin), + "Failed to get and enable clock from Device Tree\n"); + } + rc =3D of_get_ethdev_address(ofdev->dev.of_node, ndev); if (rc) { dev_warn(dev, "No MAC address found, using random\n"); --=20 2.34.1