From nobody Sun Feb 8 16:11:29 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00AF114C5B5; Sat, 10 Aug 2024 08:45:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723279521; cv=none; b=UiCLAsn7jfoBo37Xj/LSpzHBsoG8xMIjFt8w6cDBU/P/eQtV4JKPGLr1m5MXf6kj9lNZwZrpbjmOyXkVkTvH6r7052RNA6Y2geAfHlhQjVGcwwXq/ppf6CNDZ8TRiP73Up3/cmrK0ESJ+QOra07v1+EZaAXh9tCyK6JFmLvTwsw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723279521; c=relaxed/simple; bh=ilpXUuTUXGs5exW2A+RhdHqgfWS/fpbIuz78AEWYgCI=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=AfI+wx2+yW2QDKg9oUhFxRz+re+WPPB37Z13Efsa+5DWAJFGpP8SJG2tPy1Eqir7u0pOrhSLeAqrxpzazMyMIBYo2DeQ1s7LWnakzcMnUDf4ap3+X2PqlgsksSi2se5zpbXx2IlMwbPb+A0u2RQxzBb0IpsyHH/5CqLPdKNjI2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ljiuYpet; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=74XQaywc; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ljiuYpet"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="74XQaywc" Date: Sat, 10 Aug 2024 08:45:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1723279518; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qoXMfZjLY0rWS4/ESdXfLyEJcJJFrL/q2UORtfRycsE=; b=ljiuYpetE2p7mxRqnsOu3CXVVv0wxW397kSTSYSrNzVc8x1ieagvsHcBkjtVMoS3Pa5+ze 1Yu5Ayakpftf++5507xHyQK/mIA423gDw0TcyYRuot0zLR9x/ua8Zmb4u8ySF20+4sgJUY rHp6cxygrOLuopck+Cft17TUOPqPwaoX7r+Ph1HAuroYBhPze/4v+QIdMaH6MTGQ16e91D BS40BFZU2DGnz1s0vAoidrXZXEGwQGFBEd2P2BVItMwkJVKDHgKWwPTFVD1MpWCTt3Z5kk SRzTxLM0IMyWKrkT9LQwAQc5jwnUpn1URwcn2xIl5Qd7KHxGWL6ADYMFstTmbw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1723279518; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qoXMfZjLY0rWS4/ESdXfLyEJcJJFrL/q2UORtfRycsE=; b=74XQaywcfwHVzMR3xL+MwKz50ZdbeBvkIjrBhiYt2tioElH3q8zFIzufyHxp4nsrzEZ34e IqwtUnlc0SeeMTAQ== From: "tip-bot2 for Yong-Xuan Wang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/urgent] irqchip/riscv-aplic: Retrigger MSI interrupt on source configuration Cc: "Yong-Xuan Wang" , Thomas Gleixner , Vincent Chen , Anup Patel , stable@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20240809071049.2454-1-yongxuan.wang@sifive.com> References: <20240809071049.2454-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <172327951735.2215.9481646283292037219.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/urgent branch of tip: Commit-ID: 03f9885c60adf73488fe32aab628ee3d4a39598e Gitweb: https://git.kernel.org/tip/03f9885c60adf73488fe32aab628ee3d4= a39598e Author: Yong-Xuan Wang AuthorDate: Fri, 09 Aug 2024 15:10:47 +08:00 Committer: Thomas Gleixner CommitterDate: Sat, 10 Aug 2024 10:42:04 +02:00 irqchip/riscv-aplic: Retrigger MSI interrupt on source configuration The section 4.5.2 of the RISC-V AIA specification says that "any write to a sourcecfg register of an APLIC might (or might not) cause the corresponding interrupt-pending bit to be set to one if the rectified input value is high (=3D 1) under the new source mode." When the interrupt type is changed in the sourcecfg register, the APLIC device might not set the corresponding pending bit, so the interrupt might never become pending. To handle sourcecfg register changes for level-triggered interrupts in MSI mode, manually set the pending bit for retriggering interrupt so it gets retriggered if it was already asserted. Fixes: ca8df97fe679 ("irqchip/riscv-aplic: Add support for MSI-mode") Signed-off-by: Yong-Xuan Wang Signed-off-by: Thomas Gleixner Reviewed-by: Vincent Chen Reviewed-by: Anup Patel Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20240809071049.2454-1-yongxuan.wang@sifiv= e.com --- drivers/irqchip/irq-riscv-aplic-msi.c | 32 ++++++++++++++++++++------ 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-ri= scv-aplic-msi.c index 028444a..d7773f7 100644 --- a/drivers/irqchip/irq-riscv-aplic-msi.c +++ b/drivers/irqchip/irq-riscv-aplic-msi.c @@ -32,15 +32,10 @@ static void aplic_msi_irq_unmask(struct irq_data *d) aplic_irq_unmask(d); } =20 -static void aplic_msi_irq_eoi(struct irq_data *d) +static void aplic_msi_irq_retrigger_level(struct irq_data *d) { struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); =20 - /* - * EOI handling is required only for level-triggered interrupts - * when APLIC is in MSI mode. - */ - switch (irqd_get_trigger_type(d)) { case IRQ_TYPE_LEVEL_LOW: case IRQ_TYPE_LEVEL_HIGH: @@ -59,6 +54,29 @@ static void aplic_msi_irq_eoi(struct irq_data *d) } } =20 +static void aplic_msi_irq_eoi(struct irq_data *d) +{ + /* + * EOI handling is required only for level-triggered interrupts + * when APLIC is in MSI mode. + */ + aplic_msi_irq_retrigger_level(d); +} + +static int aplic_msi_irq_set_type(struct irq_data *d, unsigned int type) +{ + int rc =3D aplic_irq_set_type(d, type); + + if (rc) + return rc; + /* + * Updating sourcecfg register for level-triggered interrupts + * requires interrupt retriggering when APLIC is in MSI mode. + */ + aplic_msi_irq_retrigger_level(d); + return 0; +} + static void aplic_msi_write_msg(struct irq_data *d, struct msi_msg *msg) { unsigned int group_index, hart_index, guest_index, val; @@ -130,7 +148,7 @@ static const struct msi_domain_template aplic_msi_templ= ate =3D { .name =3D "APLIC-MSI", .irq_mask =3D aplic_msi_irq_mask, .irq_unmask =3D aplic_msi_irq_unmask, - .irq_set_type =3D aplic_irq_set_type, + .irq_set_type =3D aplic_msi_irq_set_type, .irq_eoi =3D aplic_msi_irq_eoi, #ifdef CONFIG_SMP .irq_set_affinity =3D irq_chip_set_affinity_parent,