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Fri, 9 Aug 2024 02:02:29 -0500 From: Radhey Shyam Pandey To: , CC: , , , Radhey Shyam Pandey Subject: [PATCH v2] irqchip/xilinx: Fix shift out of bounds Date: Fri, 9 Aug 2024 12:32:24 +0530 Message-ID: <1723186944-3571957-1-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044AA:EE_|IA1PR12MB7760:EE_ X-MS-Office365-Filtering-Correlation-Id: d0a66f07-cf7f-4c0f-348f-08dcb8413d6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?eexP+5668jfOwAr39ZsvhOaf9JFZnAFRYXjMPhFg9ziJwnoA5l9XJpj7lvCf?= =?us-ascii?Q?AxRP3Knu1vLEYv2FvbhcZioLWdtsY2o7d/nwtH9YjCtjT/MBXEk3Na5xjyDh?= =?us-ascii?Q?brig1AFW90sgFfzt89uG8mQHT2USElYfBpAd1tCO9Dh8VVnQK9k06Pec5hk0?= =?us-ascii?Q?VmDLU+NmSdy6+9x6SLXlpi5rmUhDCjKsVPRw348SWwGQY0Oah5yoYb+xG2M/?= =?us-ascii?Q?uwI+eFY7Z8WBOii2fRu4wzACouAy7J/l4xSVYXnPJrSCIZswv8dyvT2QFq65?= =?us-ascii?Q?vUlGuTQXUp7VVLk+ffVseU5RBSXXNJW3Z6lMhUsAku7vRFbwJNgdhvTfCqRp?= =?us-ascii?Q?Q5NitTqiXHmzQO77vGkIillzL63XLRbEhihCtciDkFWKj+yTNE5pXeb6lVmB?= =?us-ascii?Q?8qubaeVnSBhjWUguCVDcF/5IruUzGAUjrv9HSugqWdTNCrOwF0gSoh7JEpc+?= =?us-ascii?Q?K0CSg+JQZF0e2zaZqTUdyOBtZ/AXQOXLmmtvqiPTTNLgHP+X/hxmu0VbsRde?= =?us-ascii?Q?3lBnW9rjRPHUfi9TQbDYg99NONfAYn9vpb7W9QhzMJBdUotW52HC0x8rcMks?= =?us-ascii?Q?eB+BhghBudGRZ5RFr3hvoF8yNy9VRzPHoxI17FXt3Bdi7eW8wrTMkXnGNOL2?= =?us-ascii?Q?KwaWFyisB88CAFbffKdG3FbSkxpRtB0zggsm357kAv1k+/rx5t5anTmXoFUP?= =?us-ascii?Q?sSYGwJBNOSRi2D3AM2bzrou/OfctZmV1LQSVbfDMwlukqCSiolfRGAxQYK97?= =?us-ascii?Q?F2TOG3vwbrPLVQtR4T5G93sw6IcnqQlkZeLeM2zXMoVLoCyRf3VR+METCew8?= =?us-ascii?Q?SJzgTZsWBuxwwlbXvAS5jNBf9X9G8JiVpIghXeJD5y2tEkFCX7bEHC4ySVHa?= =?us-ascii?Q?6arMpnkIWM525gfknZVYV5+9B31IpH2Ute2Fzp9m2nYIhShuIOxhu37QZtKx?= =?us-ascii?Q?BfS8POfK7UFCoMWfj9h+6IwG1z9VxKj8eS+q7eC5XehvTfl8WHnC1Wmz/ezJ?= =?us-ascii?Q?NPwQZYAGOAP5ARg5Zf8L8qE/JvwDhle3xUiTI0Iqe1/ccrSCkEPSXFl0Sw/w?= =?us-ascii?Q?/n78HZFkKph5ehF7m/lYI/kw0g8v6qUFSjuCBEA/S+EMsw1jct6lqtbXdkQ7?= =?us-ascii?Q?C5G5P7sX7j6Kfdf1kU5Q0hD1cXK/hX4ejVO5Zt8bOW8n6HLpuicRWrwuxMmZ?= =?us-ascii?Q?slQgkYLTobBN1dXItsEg+c0iaF1LPDC7iPrMrEZOpQXyQpW73BWWjzXg1jX5?= =?us-ascii?Q?uJ/m2HNw8o9JgYW8F4XRUO0mhTbdg0CHHCezS/5w9sjwZxcPE4Fcc/ZwUErs?= =?us-ascii?Q?EShx53fYD/dRwIpG3vLXnWMJtatHjbgzkS/iOU5VSJkH6DpakTa4ozYm0crx?= =?us-ascii?Q?KDWXdbs31X+/fHX4gt2Bd6jVl/hCU4qXH6tSUxzRiGgo18GStWwdT630ztaU?= =?us-ascii?Q?KxWxyC+Qhy0kqkLsxCttnLUbWAetBVVv?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Aug 2024 07:02:32.0754 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0a66f07-cf7f-4c0f-348f-08dcb8413d6e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044AA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7760 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The device tree property 'xlnx,kind-of-intr' sanity checked that the bitmask contains only set bits which are in the range of the number of interrupts supported by the controller. The check is done by shifting the mask right by the number of supported interrupts and checking the result for zero. The data type of the mask is u32 and the number of supported interrupts is up to 32. In case of 32 interrupts the shift is out of bounds, resulting in a mismatch warning. The out of bounds condition is also reported by UBSAN. UBSAN: shift-out-of-bounds in irq-xilinx-intc.c:332:22 shift exponent 32 is too large for 32-bit type 'unsigned int' Fix it by promoting the mask to u64 for the test. Fixes: d50466c90724 ("microblaze: intc: Refactor DT sanity check") Signed-off-by: Radhey Shyam Pandey --- Changes for v2: Rephrase one line summary and commit description as suggested by Thomas Gleixner. --- drivers/irqchip/irq-xilinx-intc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-xilinx-intc.c b/drivers/irqchip/irq-xilinx= -intc.c index 238d3d344949..7e08714d507f 100644 --- a/drivers/irqchip/irq-xilinx-intc.c +++ b/drivers/irqchip/irq-xilinx-intc.c @@ -189,7 +189,7 @@ static int __init xilinx_intc_of_init(struct device_nod= e *intc, irqc->intr_mask =3D 0; } =20 - if (irqc->intr_mask >> irqc->nr_irq) + if ((u64)irqc->intr_mask >> irqc->nr_irq) pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); =20 pr_info("irq-xilinx: %pOF: num_irq=3D%d, edge=3D0x%x\n", base-commit: ee9a43b7cfe2d8a3520335fea7d8ce71b8cabd9d --=20 2.34.1