From nobody Wed Oct 30 22:14:33 2024 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 902421BC091; Thu, 1 Aug 2024 16:35:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722530135; cv=none; b=J2Yc2ogxr0SpDtWb/FsH+Y9uiIykRnwyRiV08DfDTAnEJkXvdIZS3ZVRDWZIHEognQadWjnI4ZKrDDBaDNHqVxKgg4Jy9vmf/PvZy4ZWdDxn+r1oT9qsjVi1iidu1Dm93qo83hO+TCNQFSZzr/qiROUHCkB9hsV6l8kX4g8VZT8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722530135; c=relaxed/simple; bh=0Lfx1WVgwRxf1gQh7kwV7t7BdlI9ig0l0ULy/fkNVLw=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Wfi21NzIBKZ0x6KS50AJoUjCA3lceqRahjwr1e/O+rhXusmvZsySk+G0cHumy4frtuBtZ3UxE3mBr0t6r08vdIYC/mKbBbUJiRzV5jCyaHVOVdOouND1utIoZGh3tf+6wSy0LAlzAwPAL1G1LJa5iIZHY0IEyy5JPqboohq6Pu4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=uSottXwt; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=crO/vnAL; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="uSottXwt"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="crO/vnAL" Date: Thu, 01 Aug 2024 16:35:31 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1722530131; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tMS6Rh4AdYXsJAxbP/xam9UWNoPS5vyVFd5JLNmBres=; b=uSottXwtkajH6kaNob23dNRPoTDx5L4v7XwVzL8I47zECFOsNxKs05Mx0S07Kb6QmyYFio S2gaRCftlob2hgQ6zD6aGqncA3jI5Fdl8KBGzp/BHThFqIUq1vJldrvoTDPqsLTZTc7fxN 8HI6sS1H4E2CnNbVWFCzhK51pV1ldsxnpgL4FBkft6mHEKvH+2dk+EOQMIrcGtI+fKyq+J uNlNrgseCZ2jIiSU8JMFUhloZB2FLtqDXctgC8M0+pP+BpHUTUUZMPB1jHDmOCGwLgHvyG IVy+tBoZ8Msxjb6gsp3eO093Q7SIKgDdh32Smgq3Q0uX2Vt+xzCilMXGrGu7iQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1722530131; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tMS6Rh4AdYXsJAxbP/xam9UWNoPS5vyVFd5JLNmBres=; b=crO/vnALldNmzddUdNYeNkdQr5SiX6wzZcPqoFv+HzQ+j+e0pLzof5s6WvjsGu3AVP6GvN bPfi8EBn+7xoB7CQ== From: "tip-bot2 for Yazen Ghannam" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: ras/core] x86/mce: Define mce_prep_record() helpers for common and per-CPU fields Cc: Yazen Ghannam , "Borislav Petkov (AMD)" , Nikolay Borisov , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20240730182958.4117158-3-yazen.ghannam@amd.com> References: <20240730182958.4117158-3-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <172253013144.2215.3708689740044304266.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the ras/core branch of tip: Commit-ID: f9bbb8ad0c8b2f37e3d474b8693f563e4a29e92e Gitweb: https://git.kernel.org/tip/f9bbb8ad0c8b2f37e3d474b8693f563e4= a29e92e Author: Yazen Ghannam AuthorDate: Tue, 30 Jul 2024 13:29:57 -05:00 Committer: Borislav Petkov (AMD) CommitterDate: Thu, 01 Aug 2024 18:20:25 +02:00 x86/mce: Define mce_prep_record() helpers for common and per-CPU fields Generally, MCA information for an error is gathered on the CPU that reported the error. In this case, CPU-specific information from the running CPU will be correct. However, this will be incorrect if the MCA information is gathered while running on a CPU that didn't report the error. One example is creating an MCA record using mce_prep_record() for errors reported from ACPI. Split mce_prep_record() so that there is a helper function to gather common, i.e. not CPU-specific, information and another helper for CPU-specific information. Leave mce_prep_record() defined as-is for the common case when running on the reporting CPU. Get MCG_CAP in the global helper even though the register is per-CPU. This value is not already cached per-CPU like other values. And it does not assist with any per-CPU decoding or handling. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Nikolay Borisov Link: https://lore.kernel.org/r/20240730182958.4117158-3-yazen.ghannam@amd.= com Signed-off-by: Borislav Petkov (AMD) --- arch/x86/kernel/cpu/mce/core.c | 34 +++++++++++++++++++---------- arch/x86/kernel/cpu/mce/internal.h | 2 ++- 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index dd5192e..2a938f4 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -117,20 +117,32 @@ static struct irq_work mce_irq_work; */ BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); =20 -/* Do initial initialization of a struct mce */ -void mce_prep_record(struct mce *m) +void mce_prep_record_common(struct mce *m) { memset(m, 0, sizeof(struct mce)); - m->cpu =3D m->extcpu =3D smp_processor_id(); + + m->cpuid =3D cpuid_eax(1); + m->cpuvendor =3D boot_cpu_data.x86_vendor; + m->mcgcap =3D __rdmsr(MSR_IA32_MCG_CAP); /* need the internal __ version to avoid deadlocks */ - m->time =3D __ktime_get_real_seconds(); - m->cpuvendor =3D boot_cpu_data.x86_vendor; - m->cpuid =3D cpuid_eax(1); - m->socketid =3D cpu_data(m->extcpu).topo.pkg_id; - m->apicid =3D cpu_data(m->extcpu).topo.initial_apicid; - m->mcgcap =3D __rdmsr(MSR_IA32_MCG_CAP); - m->ppin =3D cpu_data(m->extcpu).ppin; - m->microcode =3D boot_cpu_data.microcode; + m->time =3D __ktime_get_real_seconds(); +} + +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m) +{ + m->cpu =3D cpu; + m->extcpu =3D cpu; + m->apicid =3D cpu_data(cpu).topo.initial_apicid; + m->microcode =3D cpu_data(cpu).microcode; + m->ppin =3D topology_ppin(cpu); + m->socketid =3D topology_physical_package_id(cpu); +} + +/* Do initial initialization of a struct mce */ +void mce_prep_record(struct mce *m) +{ + mce_prep_record_common(m); + mce_prep_record_per_cpu(smp_processor_id(), m); } =20 DEFINE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index 01f8f03..43c7f3b 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -261,6 +261,8 @@ enum mca_msr { =20 /* Decide whether to add MCE record to MCE event pool or filter it out. */ extern bool filter_mce(struct mce *m); +void mce_prep_record_common(struct mce *m); +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m); =20 #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m);