From nobody Tue Dec 16 17:55:19 2025 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3433E146D6C; Fri, 19 Jul 2024 06:01:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368883; cv=none; b=YcBKixndPNlHTA9GKCrNT6VxJCiHlsM0/fOxMJPZsVX2dmeyie9XtG5mVDEOhcEyOinrMReDLxpR7ZjRyHcdNGK3mh0CamR8LMt98mXRnQ4Si6sAck4vlBjkig4rT3ziq17WpAz/qJxLY9UDi0JUfd52K6jHfr/wZx312oisPYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368883; c=relaxed/simple; bh=Tt99vW0yPGRlG70EaM0HA3UHhbwRYeYBF2lX+BqlYa8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=ZgvCxj+pFF0lBgvWqa7odRhTr7tK2/wWuN6h1TtXX3lKhy2EqzN/Ya5KzDCn6KbIztz+HU6xPjHyBRhPbDFw83nPf8J7u3BEM6TmrztH6wU15KfG1Hd0835ed+sA2ZiAgpO0kliGjJwW6TDWwzjKgQaxb11oyV3X/ZMrx5DAsbI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A0034200D1F; Fri, 19 Jul 2024 08:01:15 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 66FF82015E2; Fri, 19 Jul 2024 08:01:15 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id C2E49181D0FE; Fri, 19 Jul 2024 14:01:13 +0800 (+08) From: Richard Zhu To: tj@kernel.org, dlemoal@kernel.org, cassel@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com Cc: linux-ide@vger.kernel.org, stable@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, kernel@pengutronix.de, Richard Zhu Subject: [PATCH v4 1/6] dt-bindings: ata: Add i.MX8QM AHCI compatible string Date: Fri, 19 Jul 2024 13:42:11 +0800 Message-Id: <1721367736-30156-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> References: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8QM AHCI "fsl,imx8qm-ahci" compatible strings. i.MX8QM AHCI SATA doesn't require AHB clock rate to set the vendor specified TIMER1MS register. ahb clock is not required by i.MX8QM AHCI. Update the description of clocks in the dt-binding accordingly. Signed-off-by: Richard Zhu Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/ata/imx-sata.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/imx-sata.yaml b/Document= ation/devicetree/bindings/ata/imx-sata.yaml index 68ffb97ddc9b2..f4eb3550a0960 100644 --- a/Documentation/devicetree/bindings/ata/imx-sata.yaml +++ b/Documentation/devicetree/bindings/ata/imx-sata.yaml @@ -19,6 +19,7 @@ properties: - fsl,imx53-ahci - fsl,imx6q-ahci - fsl,imx6qp-ahci + - fsl,imx8qm-ahci =20 reg: maxItems: 1 @@ -27,12 +28,14 @@ properties: maxItems: 1 =20 clocks: + minItems: 2 items: - description: sata clock - description: sata reference clock - description: ahb clock =20 clock-names: + minItems: 2 items: - const: sata - const: sata_ref @@ -58,6 +61,25 @@ properties: $ref: /schemas/types.yaml#/definitions/flag description: if present, disable spread-spectrum clocking on the SATA = link. =20 + phys: + items: + - description: phandle to SATA PHY. + Since "REXT" pin is only present for first lane of i.MX8QM PHY, = it's + calibration result will be stored, passed through second lane, a= nd + shared with all three lanes PHY. The first two lanes PHY are use= d as + calibration PHYs, although only the third lane PHY is used by SA= TA. + - description: phandle to the first lane PHY of i.MX8QM. + - description: phandle to the second lane PHY of i.MX8QM. + + phy-names: + items: + - const: sata-phy + - const: cali-phy0 + - const: cali-phy1 + + power-domains: + maxItems: 1 + required: - compatible - reg @@ -65,6 +87,31 @@ required: - clocks - clock-names =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx53-ahci + - fsl,imx6q-ahci + - fsl,imx6qp-ahci + then: + properties: + clock-names: + minItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-ahci + then: + properties: + clock-names: + minItems: 2 + additionalProperties: false =20 examples: --=20 2.37.1 From nobody Tue Dec 16 17:55:19 2025 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 941C814831C; Fri, 19 Jul 2024 06:01:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368887; cv=none; b=WjqsEMuVj64h60Mz5ptCTr1rQi1Bu2RSLGBuMo0YivurXT2uMR+DuPM4l9GOr+eOADrR+rMppTTLveJDk+qnQU7f3S3t/asx1HD9xbgu8SLfbNGPzpMid922Zd35hy/lOVJ+JWgsF50clH8/nkmVYPJIPZ1v7L53FhrEOCdHXVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368887; c=relaxed/simple; bh=1766+04ZgFm/F1vZX4/9ie+I5nhRwku8Nn9ttdzdfmA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=JiNQnq+HLoKSfFDxVY91gcKgN4kHnq8yiETv5RMvs39w9ublvXnUT3uXcDWpP62V22M3D28obPK6QvAXB48njK3BuSg75pGSDTfxlFWSWG3rEezjCRFW7fbHDGPI60jw3TSUcugKZXOlAMlxEUafs7ObdSE3EkFibw2M2k2XUP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 912B41A12F6; Fri, 19 Jul 2024 08:01:17 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3987E1A12EC; Fri, 19 Jul 2024 08:01:17 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 479321820F57; Fri, 19 Jul 2024 14:01:15 +0800 (+08) From: Richard Zhu To: tj@kernel.org, dlemoal@kernel.org, cassel@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com Cc: linux-ide@vger.kernel.org, stable@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, kernel@pengutronix.de, Richard Zhu Subject: [PATCH v4 2/6] ata: ahci_imx: Clean up code by using i.MX8Q HSIO PHY driver Date: Fri, 19 Jul 2024 13:42:12 +0800 Message-Id: <1721367736-30156-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> References: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Clean up code by using PHY interface provided by the PHY driver under PHY subsystem(drivers/phy/freescale/phy-fsl-imx8qm-hsio.c). Signed-off-by: Richard Zhu --- drivers/ata/ahci_imx.c | 365 +++++++++-------------------------------- 1 file changed, 80 insertions(+), 285 deletions(-) diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index cb768f66f0a70..75258ed42d2ee 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "ahci.h" =20 @@ -44,42 +45,6 @@ enum { /* Clock Reset Register */ IMX_CLOCK_RESET =3D 0x7f3f, IMX_CLOCK_RESET_RESET =3D 1 << 0, - /* IMX8QM HSIO AHCI definitions */ - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET =3D 0x03, - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET =3D 0x09, - IMX8QM_SATA_PHY_IMPED_RATIO_85OHM =3D 0x6c, - IMX8QM_LPCG_PHYX2_OFFSET =3D 0x00000, - IMX8QM_CSR_PHYX2_OFFSET =3D 0x90000, - IMX8QM_CSR_PHYX1_OFFSET =3D 0xa0000, - IMX8QM_CSR_PHYX_STTS0_OFFSET =3D 0x4, - IMX8QM_CSR_PCIEA_OFFSET =3D 0xb0000, - IMX8QM_CSR_PCIEB_OFFSET =3D 0xc0000, - IMX8QM_CSR_SATA_OFFSET =3D 0xd0000, - IMX8QM_CSR_PCIE_CTRL2_OFFSET =3D 0x8, - IMX8QM_CSR_MISC_OFFSET =3D 0xe0000, - - IMX8QM_LPCG_PHYX2_PCLK0_MASK =3D (0x3 << 16), - IMX8QM_LPCG_PHYX2_PCLK1_MASK =3D (0x3 << 20), - IMX8QM_PHY_APB_RSTN_0 =3D BIT(0), - IMX8QM_PHY_MODE_SATA =3D BIT(19), - IMX8QM_PHY_MODE_MASK =3D (0xf << 17), - IMX8QM_PHY_PIPE_RSTN_0 =3D BIT(24), - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 =3D BIT(25), - IMX8QM_PHY_PIPE_RSTN_1 =3D BIT(26), - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 =3D BIT(27), - IMX8QM_STTS0_LANE0_TX_PLL_LOCK =3D BIT(4), - IMX8QM_MISC_IOB_RXENA =3D BIT(0), - IMX8QM_MISC_IOB_TXENA =3D BIT(1), - IMX8QM_MISC_PHYX1_EPCS_SEL =3D BIT(12), - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 =3D BIT(24), - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 =3D BIT(25), - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 =3D BIT(28), - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 =3D BIT(29), - IMX8QM_SATA_CTRL_RESET_N =3D BIT(12), - IMX8QM_SATA_CTRL_EPCS_PHYRESET_N =3D BIT(7), - IMX8QM_CTRL_BUTTON_RST_N =3D BIT(21), - IMX8QM_CTRL_POWER_UP_RST_N =3D BIT(23), - IMX8QM_CTRL_LTSSM_ENABLE =3D BIT(4), }; =20 enum ahci_imx_type { @@ -95,14 +60,10 @@ struct imx_ahci_priv { struct clk *sata_clk; struct clk *sata_ref_clk; struct clk *ahb_clk; - struct clk *epcs_tx_clk; - struct clk *epcs_rx_clk; - struct clk *phy_apbclk; - struct clk *phy_pclk0; - struct clk *phy_pclk1; - void __iomem *phy_base; - struct gpio_desc *clkreq_gpiod; struct regmap *gpr; + struct phy *sata_phy; + struct phy *cali_phy0; + struct phy *cali_phy1; bool no_device; bool first_time; u32 phy_params; @@ -450,201 +411,73 @@ ATTRIBUTE_GROUPS(fsl_sata_ahci); =20 static int imx8_sata_enable(struct ahci_host_priv *hpriv) { - u32 val, reg; - int i, ret; + u32 val; + int ret; struct imx_ahci_priv *imxpriv =3D hpriv->plat_data; struct device *dev =3D &imxpriv->ahci_pdev->dev; =20 - /* configure the hsio for sata */ - ret =3D clk_prepare_enable(imxpriv->phy_pclk0); - if (ret < 0) { - dev_err(dev, "can't enable phy_pclk0.\n"); + /* + * Since "REXT" pin is only present for first lane of i.MX8QM + * PHY, its calibration results will be stored, passed through + * to the second lane PHY, and shared with all three lane PHYs. + * + * Initialize the first two lane PHYs here, although only the + * third lane PHY is used by SATA. + */ + ret =3D phy_init(imxpriv->cali_phy0); + if (ret) { + dev_err(dev, "cali PHY init failed\n"); return ret; } - ret =3D clk_prepare_enable(imxpriv->phy_pclk1); - if (ret < 0) { - dev_err(dev, "can't enable phy_pclk1.\n"); - goto disable_phy_pclk0; + ret =3D phy_power_on(imxpriv->cali_phy0); + if (ret) { + dev_err(dev, "cali PHY power on failed\n"); + goto err_cali_phy0_exit; } - ret =3D clk_prepare_enable(imxpriv->epcs_tx_clk); - if (ret < 0) { - dev_err(dev, "can't enable epcs_tx_clk.\n"); - goto disable_phy_pclk1; + ret =3D phy_init(imxpriv->cali_phy1); + if (ret) { + dev_err(dev, "cali PHY1 init failed\n"); + goto err_cali_phy0_off; } - ret =3D clk_prepare_enable(imxpriv->epcs_rx_clk); - if (ret < 0) { - dev_err(dev, "can't enable epcs_rx_clk.\n"); - goto disable_epcs_tx_clk; + ret =3D phy_power_on(imxpriv->cali_phy1); + if (ret) { + dev_err(dev, "cali PHY1 power on failed\n"); + goto err_cali_phy1_exit; } - ret =3D clk_prepare_enable(imxpriv->phy_apbclk); - if (ret < 0) { - dev_err(dev, "can't enable phy_apbclk.\n"); - goto disable_epcs_rx_clk; + ret =3D phy_init(imxpriv->sata_phy); + if (ret) { + dev_err(dev, "sata PHY init failed\n"); + goto err_cali_phy1_off; } - /* Configure PHYx2 PIPE_RSTN */ - regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET + - IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val); - if ((val & IMX8QM_CTRL_LTSSM_ENABLE) =3D=3D 0) { - /* The link of the PCIEA of HSIO is down */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX2_OFFSET, - IMX8QM_PHY_PIPE_RSTN_0 | - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0, - IMX8QM_PHY_PIPE_RSTN_0 | - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0); + ret =3D phy_set_mode(imxpriv->sata_phy, PHY_MODE_SATA); + if (ret) { + dev_err(dev, "unable to set SATA PHY mode\n"); + goto err_sata_phy_exit; } - regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET + - IMX8QM_CSR_PCIE_CTRL2_OFFSET, ®); - if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) =3D=3D 0) { - /* The link of the PCIEB of HSIO is down */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX2_OFFSET, - IMX8QM_PHY_PIPE_RSTN_1 | - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1, - IMX8QM_PHY_PIPE_RSTN_1 | - IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1); - } - if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) =3D=3D 0) { - /* The links of both PCIA and PCIEB of HSIO are down */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_LPCG_PHYX2_OFFSET, - IMX8QM_LPCG_PHYX2_PCLK0_MASK | - IMX8QM_LPCG_PHYX2_PCLK1_MASK, - 0); + ret =3D phy_power_on(imxpriv->sata_phy); + if (ret) { + dev_err(dev, "sata PHY power up failed\n"); + goto err_sata_phy_exit; } =20 - /* set PWR_RST and BT_RST of csr_pciea */ - val =3D IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET; - regmap_update_bits(imxpriv->gpr, - val, - IMX8QM_CTRL_BUTTON_RST_N, - IMX8QM_CTRL_BUTTON_RST_N); - regmap_update_bits(imxpriv->gpr, - val, - IMX8QM_CTRL_POWER_UP_RST_N, - IMX8QM_CTRL_POWER_UP_RST_N); - - /* PHYX1_MODE to SATA */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX1_OFFSET, - IMX8QM_PHY_MODE_MASK, - IMX8QM_PHY_MODE_SATA); + /* The cali_phy# can be turned off after SATA PHY is initialized. */ + phy_power_off(imxpriv->cali_phy1); + phy_exit(imxpriv->cali_phy1); + phy_power_off(imxpriv->cali_phy0); + phy_exit(imxpriv->cali_phy0); =20 - /* - * BIT0 RXENA 1, BIT1 TXENA 0 - * BIT12 PHY_X1_EPCS_SEL 1. - */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_IOB_RXENA, - IMX8QM_MISC_IOB_RXENA); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_IOB_TXENA, - 0); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_PHYX1_EPCS_SEL, - IMX8QM_MISC_PHYX1_EPCS_SEL); - /* - * It is possible, for PCIe and SATA are sharing - * the same clock source, HPLL or external oscillator. - * When PCIe is in low power modes (L1.X or L2 etc), - * the clock source can be turned off. In this case, - * if this clock source is required to be toggling by - * SATA, then SATA functions will be abnormal. - * Set the override here to avoid it. - */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_MISC_OFFSET, - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 | - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 | - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 | - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0, - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 | - IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 | - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 | - IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0); - - /* clear PHY RST, then set it */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_EPCS_PHYRESET_N, - 0); - - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_EPCS_PHYRESET_N, - IMX8QM_SATA_CTRL_EPCS_PHYRESET_N); - - /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_RESET_N, - IMX8QM_SATA_CTRL_RESET_N); - udelay(1); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_RESET_N, - 0); - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_SATA_OFFSET, - IMX8QM_SATA_CTRL_RESET_N, - IMX8QM_SATA_CTRL_RESET_N); - - /* APB reset */ - regmap_update_bits(imxpriv->gpr, - IMX8QM_CSR_PHYX1_OFFSET, - IMX8QM_PHY_APB_RSTN_0, - IMX8QM_PHY_APB_RSTN_0); - - for (i =3D 0; i < 100; i++) { - reg =3D IMX8QM_CSR_PHYX1_OFFSET + - IMX8QM_CSR_PHYX_STTS0_OFFSET; - regmap_read(imxpriv->gpr, reg, &val); - val &=3D IMX8QM_STTS0_LANE0_TX_PLL_LOCK; - if (val =3D=3D IMX8QM_STTS0_LANE0_TX_PLL_LOCK) - break; - udelay(1); - } - - if (val !=3D IMX8QM_STTS0_LANE0_TX_PLL_LOCK) { - dev_err(dev, "TX PLL of the PHY is not locked\n"); - ret =3D -ENODEV; - } else { - writeb(imxpriv->imped_ratio, imxpriv->phy_base + - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET); - writeb(imxpriv->imped_ratio, imxpriv->phy_base + - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET); - reg =3D readb(imxpriv->phy_base + - IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET); - if (unlikely(reg !=3D imxpriv->imped_ratio)) - dev_info(dev, "Can't set PHY RX impedance ratio.\n"); - reg =3D readb(imxpriv->phy_base + - IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET); - if (unlikely(reg !=3D imxpriv->imped_ratio)) - dev_info(dev, "Can't set PHY TX impedance ratio.\n"); - usleep_range(50, 100); - - /* - * To reduce the power consumption, gate off - * the PHY clks - */ - clk_disable_unprepare(imxpriv->phy_apbclk); - clk_disable_unprepare(imxpriv->phy_pclk1); - clk_disable_unprepare(imxpriv->phy_pclk0); - return ret; - } + return 0; =20 - clk_disable_unprepare(imxpriv->phy_apbclk); -disable_epcs_rx_clk: - clk_disable_unprepare(imxpriv->epcs_rx_clk); -disable_epcs_tx_clk: - clk_disable_unprepare(imxpriv->epcs_tx_clk); -disable_phy_pclk1: - clk_disable_unprepare(imxpriv->phy_pclk1); -disable_phy_pclk0: - clk_disable_unprepare(imxpriv->phy_pclk0); +err_sata_phy_exit: + phy_exit(imxpriv->sata_phy); +err_cali_phy1_off: + phy_power_off(imxpriv->cali_phy1); +err_cali_phy1_exit: + phy_exit(imxpriv->cali_phy1); +err_cali_phy0_off: + phy_power_off(imxpriv->cali_phy0); +err_cali_phy0_exit: + phy_exit(imxpriv->cali_phy0); =20 return ret; } @@ -698,6 +531,9 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv) } } else if (imxpriv->type =3D=3D AHCI_IMX8QM) { ret =3D imx8_sata_enable(hpriv); + if (ret) + goto disable_clk; + } =20 usleep_range(1000, 2000); @@ -736,8 +572,10 @@ static void imx_sata_disable(struct ahci_host_priv *hp= riv) break; =20 case AHCI_IMX8QM: - clk_disable_unprepare(imxpriv->epcs_rx_clk); - clk_disable_unprepare(imxpriv->epcs_tx_clk); + if (imxpriv->sata_phy) { + phy_power_off(imxpriv->sata_phy); + phy_exit(imxpriv->sata_phy); + } break; =20 default: @@ -760,6 +598,9 @@ static void ahci_imx_error_handler(struct ata_port *ap) =20 ahci_error_handler(ap); =20 + if (imxpriv->type =3D=3D AHCI_IMX8QM) + return; + if (!(imxpriv->first_time) || ahci_imx_hotplug) return; =20 @@ -986,65 +827,19 @@ static const struct scsi_host_template ahci_platform_= sht =3D { =20 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpr= iv) { - struct resource *phy_res; - struct platform_device *pdev =3D imxpriv->ahci_pdev; - struct device_node *np =3D dev->of_node; - - if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio)) - imxpriv->imped_ratio =3D IMX8QM_SATA_PHY_IMPED_RATIO_85OHM; - phy_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); - if (phy_res) { - imxpriv->phy_base =3D devm_ioremap(dev, phy_res->start, - resource_size(phy_res)); - if (!imxpriv->phy_base) { - dev_err(dev, "error with ioremap\n"); - return -ENOMEM; - } - } else { - dev_err(dev, "missing *phy* reg region.\n"); - return -ENOMEM; - } - imxpriv->gpr =3D - syscon_regmap_lookup_by_phandle(np, "hsio"); - if (IS_ERR(imxpriv->gpr)) { - dev_err(dev, "unable to find gpr registers\n"); - return PTR_ERR(imxpriv->gpr); - } - - imxpriv->epcs_tx_clk =3D devm_clk_get(dev, "epcs_tx"); - if (IS_ERR(imxpriv->epcs_tx_clk)) { - dev_err(dev, "can't get epcs_tx_clk clock.\n"); - return PTR_ERR(imxpriv->epcs_tx_clk); - } - imxpriv->epcs_rx_clk =3D devm_clk_get(dev, "epcs_rx"); - if (IS_ERR(imxpriv->epcs_rx_clk)) { - dev_err(dev, "can't get epcs_rx_clk clock.\n"); - return PTR_ERR(imxpriv->epcs_rx_clk); - } - imxpriv->phy_pclk0 =3D devm_clk_get(dev, "phy_pclk0"); - if (IS_ERR(imxpriv->phy_pclk0)) { - dev_err(dev, "can't get phy_pclk0 clock.\n"); - return PTR_ERR(imxpriv->phy_pclk0); - } - imxpriv->phy_pclk1 =3D devm_clk_get(dev, "phy_pclk1"); - if (IS_ERR(imxpriv->phy_pclk1)) { - dev_err(dev, "can't get phy_pclk1 clock.\n"); - return PTR_ERR(imxpriv->phy_pclk1); - } - imxpriv->phy_apbclk =3D devm_clk_get(dev, "phy_apbclk"); - if (IS_ERR(imxpriv->phy_apbclk)) { - dev_err(dev, "can't get phy_apbclk clock.\n"); - return PTR_ERR(imxpriv->phy_apbclk); - } - - /* Fetch GPIO, then enable the external OSC */ - imxpriv->clkreq_gpiod =3D devm_gpiod_get_optional(dev, "clkreq", - GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE); - if (IS_ERR(imxpriv->clkreq_gpiod)) - return PTR_ERR(imxpriv->clkreq_gpiod); - if (imxpriv->clkreq_gpiod) - gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ"); - + imxpriv->sata_phy =3D devm_phy_get(dev, "sata-phy"); + if (IS_ERR(imxpriv->sata_phy)) + return dev_err_probe(dev, PTR_ERR(imxpriv->sata_phy), + "Failed to get sata_phy\n"); + + imxpriv->cali_phy0 =3D devm_phy_get(dev, "cali-phy0"); + if (IS_ERR(imxpriv->cali_phy0)) + return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy0), + "Failed to get cali_phy0\n"); + imxpriv->cali_phy1 =3D devm_phy_get(dev, "cali-phy1"); + if (IS_ERR(imxpriv->cali_phy1)) + return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy1), + "Failed to get cali_phy1\n"); return 0; } =20 --=20 2.37.1 From nobody Tue Dec 16 17:55:19 2025 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 417F37BAE3; Fri, 19 Jul 2024 06:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368888; cv=none; b=icEW8XaGkBrxzCK/MzgzBEhP/jdLM/Anq3BSGl7DrVZHj2mRMpDuVHueHrBhh89PtCjkysWUpR0UhE93jsMFDSh8Mxp5a4OhYPcET9SU904LmVz1SCZT4bOp4N+SHMC6sXX28VVX/9X4oYOv7XzM6uayU2SMZhrDQORMNSTFLQQ= ARC-Message-Signature: i=1; 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Fri, 19 Jul 2024 08:01:18 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id BD1DA181D0FE; Fri, 19 Jul 2024 14:01:16 +0800 (+08) From: Richard Zhu To: tj@kernel.org, dlemoal@kernel.org, cassel@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com Cc: linux-ide@vger.kernel.org, stable@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, kernel@pengutronix.de, Richard Zhu Subject: [PATCH v4 3/6] ata: ahci_imx: AHB clock rate setting is not required on i.MX8QM AHCI SATA Date: Fri, 19 Jul 2024 13:42:13 +0800 Message-Id: <1721367736-30156-4-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> References: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" i.MX8QM AHCI SATA doesn't need AHB clock rate to set the vendor specified TIMER1MS register. Do the AHB clock rate setting for i.MX53 and i.MX6Q AHCI SATA only. Signed-off-by: Richard Zhu --- drivers/ata/ahci_imx.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index 75258ed42d2ee..4dd98368f8562 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -872,12 +872,6 @@ static int imx_ahci_probe(struct platform_device *pdev) return PTR_ERR(imxpriv->sata_ref_clk); } =20 - imxpriv->ahb_clk =3D devm_clk_get(dev, "ahb"); - if (IS_ERR(imxpriv->ahb_clk)) { - dev_err(dev, "can't get ahb clock.\n"); - return PTR_ERR(imxpriv->ahb_clk); - } - if (imxpriv->type =3D=3D AHCI_IMX6Q || imxpriv->type =3D=3D AHCI_IMX6QP) { u32 reg_value; =20 @@ -937,11 +931,8 @@ static int imx_ahci_probe(struct platform_device *pdev) goto disable_clk; =20 /* - * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, - * and IP vendor specific register IMX_TIMER1MS. - * Configure CAP_SSS (support stagered spin up). - * Implement the port0. - * Get the ahb clock rate, and configure the TIMER1MS register. + * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL. + * Set CAP_SSS (support stagered spin up) and Implement the port0. */ reg_val =3D readl(hpriv->mmio + HOST_CAP); if (!(reg_val & HOST_CAP_SSS)) { @@ -954,8 +945,19 @@ static int imx_ahci_probe(struct platform_device *pdev) writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL); } =20 - reg_val =3D clk_get_rate(imxpriv->ahb_clk) / 1000; - writel(reg_val, hpriv->mmio + IMX_TIMER1MS); + if (imxpriv->type !=3D AHCI_IMX8QM) { + /* + * Get AHB clock rate and configure the vendor specified + * TIMER1MS register on i.MX53, i.MX6Q and i.MX6QP only. + */ + imxpriv->ahb_clk =3D devm_clk_get(dev, "ahb"); + if (IS_ERR(imxpriv->ahb_clk)) { + dev_err(dev, "Failed to get ahb clock\n"); + goto disable_sata; + } + reg_val =3D clk_get_rate(imxpriv->ahb_clk) / 1000; + writel(reg_val, hpriv->mmio + IMX_TIMER1MS); + } =20 ret =3D ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, &ahci_platform_sht); --=20 2.37.1 From nobody Tue Dec 16 17:55:19 2025 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8AEB12F37C; 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dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 71D7E2015E7; Fri, 19 Jul 2024 08:01:20 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 41954202707; Fri, 19 Jul 2024 08:01:20 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 3F2E01820F57; Fri, 19 Jul 2024 14:01:18 +0800 (+08) From: Richard Zhu To: tj@kernel.org, dlemoal@kernel.org, cassel@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com Cc: linux-ide@vger.kernel.org, stable@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, kernel@pengutronix.de, Richard Zhu Subject: [PATCH v4 4/6] ata: ahci_imx: Add 32bits DMA limit for i.MX8QM AHCI SATA Date: Fri, 19 Jul 2024 13:42:14 +0800 Message-Id: <1721367736-30156-5-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> References: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since i.MX8QM AHCI SATA only has 32bits DMA capability. Add 32bits DMA limit here. Signed-off-by: Richard Zhu --- drivers/ata/ahci_imx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index 4dd98368f8562..e94c0fdea2260 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -827,6 +827,9 @@ static const struct scsi_host_template ahci_platform_sh= t =3D { =20 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpr= iv) { + if (!(dev->bus_dma_limit)) + dev->bus_dma_limit =3D DMA_BIT_MASK(32); + imxpriv->sata_phy =3D devm_phy_get(dev, "sata-phy"); if (IS_ERR(imxpriv->sata_phy)) return dev_err_probe(dev, PTR_ERR(imxpriv->sata_phy), --=20 2.37.1 From nobody Tue Dec 16 17:55:19 2025 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33028148850; Fri, 19 Jul 2024 06:01:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368891; cv=none; b=IGx2A24fvK8iCbl+XCWN4Tk3Tw7VdTQath7164zzetMdS/5sdCKltPgsOE2KUJNDKudwCl3h9zchPRF1UtsqXWcZUxn6CdVZUGS6ZaFzOB+08EVi+r9Vxz5tsYDbrHQcFQtykV+WEwv5mgjiiJm8c0+U5dbJB4kxHEAOlS49l3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368891; c=relaxed/simple; bh=pA6k4V9dwaoeIp5xyfNNE1f4Xu/kAiokzrri2F4N/yE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=oI5Bqjz9Mj0gnfnkxs0em52zX3oAUDvEeRc7qGRyGSSWgvt2RNZwhUG++IZYPDCiBJy1lAQK08z8wbEqe7SCbnXeEfp77rH3aBwu36DIz4rc+bsbV2JeVHNmcLUwXqODKkJDw/lxAn771rA5iZ5a+NJVkrSVSIabM1SyE3p49nQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E664C1A0264; Fri, 19 Jul 2024 08:01:21 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B41D41A01B8; Fri, 19 Jul 2024 08:01:21 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id BF6571820F77; Fri, 19 Jul 2024 14:01:19 +0800 (+08) From: Richard Zhu To: tj@kernel.org, dlemoal@kernel.org, cassel@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com Cc: linux-ide@vger.kernel.org, stable@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, kernel@pengutronix.de, Richard Zhu Subject: [PATCH v4 5/6] ata: ahci_imx: Enlarge RX water mark for i.MX8QM SATA Date: Fri, 19 Jul 2024 13:42:15 +0800 Message-Id: <1721367736-30156-6-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> References: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The RXWM(RxWaterMark) sets the minimum number of free location within the RX FIFO before the watermark is exceeded which in turn will cause the Transport Layer to instruct the Link Layer to transmit HOLDS to the transmitting end. Based on the default RXWM value 0x20, RX FIFO overflow might be observed on i.MX8QM MEK board, when some Gen3 SATA disks are used. The FIFO overflow will result in CRC error, internal error and protocol error, then the SATA link is not stable anymore. To fix this issue, enlarge RX water mark setting from 0x20 to 0x29. Signed-off-by: Richard Zhu --- drivers/ata/ahci_imx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index e94c0fdea2260..b6ad0fe5fbbcc 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -45,6 +45,10 @@ enum { /* Clock Reset Register */ IMX_CLOCK_RESET =3D 0x7f3f, IMX_CLOCK_RESET_RESET =3D 1 << 0, + /* IMX8QM SATA specific control registers */ + IMX8QM_SATA_AHCI_PTC =3D 0xc8, + IMX8QM_SATA_AHCI_PTC_RXWM_MASK =3D GENMASK(6, 0), + IMX8QM_SATA_AHCI_PTC_RXWM =3D 0x29, }; =20 enum ahci_imx_type { @@ -466,6 +470,12 @@ static int imx8_sata_enable(struct ahci_host_priv *hpr= iv) phy_power_off(imxpriv->cali_phy0); phy_exit(imxpriv->cali_phy0); =20 + /* RxWaterMark setting */ + val =3D readl(hpriv->mmio + IMX8QM_SATA_AHCI_PTC); + val &=3D ~IMX8QM_SATA_AHCI_PTC_RXWM_MASK; + val |=3D IMX8QM_SATA_AHCI_PTC_RXWM; + writel(val, hpriv->mmio + IMX8QM_SATA_AHCI_PTC); + return 0; =20 err_sata_phy_exit: --=20 2.37.1 From nobody Tue Dec 16 17:55:19 2025 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D6C91487C9; Fri, 19 Jul 2024 06:01:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368887; cv=none; b=cif+UXB9U00i95om93AjzpsSC1FhyfCqq4TJ6T2npRfJWVvIcqPd7KpnTVixqj0Zc/p5jruwHiadasko8hhGhueSiFs57cExUSejHHFPHoXElS4i4WDGpceSvgKbHtbsEypgICmNT/OQME8UyqBeDNRnGc3Yzid0On1jbU7t6K4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721368887; c=relaxed/simple; bh=K6Es3M0LOa/W0gyl83mVOEgzXNqpRKkL4E6g7DtzYh0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=U6lECSZ2iI+35lzqia6aNEmcVhKCnkBAZNVP1tCk8OLCtaSMMftXS/XGchuiKARidNbQPKxgN0eVrl2IDwdtPxeXlZRF5qMM6Gaj7WLnHwZTle6KNcyFGZvQ0J1qnIQpmnpIX/1I6N7ZeblAyIp4eaUx5ZTVw/SE5AxfXoRymJQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7FD002015F1; Fri, 19 Jul 2024 08:01:23 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 42AE42015E6; Fri, 19 Jul 2024 08:01:23 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 42DD81820F57; Fri, 19 Jul 2024 14:01:21 +0800 (+08) From: Richard Zhu To: tj@kernel.org, dlemoal@kernel.org, cassel@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com Cc: linux-ide@vger.kernel.org, stable@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, kernel@pengutronix.de, Richard Zhu Subject: [PATCH v4 6/6] ata: ahci_imx: Correct the email address Date: Fri, 19 Jul 2024 13:42:16 +0800 Message-Id: <1721367736-30156-7-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> References: <1721367736-30156-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Correct the email address of driver author. Signed-off-by: Richard Zhu --- drivers/ata/ahci_imx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index b6ad0fe5fbbcc..965466c7a27e5 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -1039,6 +1039,6 @@ static struct platform_driver imx_ahci_driver =3D { module_platform_driver(imx_ahci_driver); =20 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver"); -MODULE_AUTHOR("Richard Zhu "); +MODULE_AUTHOR("Richard Zhu "); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:" DRV_NAME); --=20 2.37.1