From nobody Wed Dec 17 15:36:23 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7561F1586C4; Tue, 9 Jul 2024 11:41:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720525319; cv=none; b=h5b0lpcHFexUpjvObCu5Ve1VgEMBW6hcwoCHd03ETCh2FrXCmImfXC2srxaTTx6Q5kDdz0L69O4/TZZkyg3G7iNUa6NUJ9440u77VXsib00tQJ+6UT3uN4xMeC0qeexza3rme5jQPanInYJDZPZGjTWptLw5XdeWIbopwIMuoOM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720525319; c=relaxed/simple; bh=KI4RKTHYnAL+XQXSsiPbfpOIsEbcNLot8g8LFEMIlz0=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=jdBEd/3yrslghGkWSR4BYhLylb2NFmzoDLaMIr60ofIxQ+hzKv8IFGRUnZaq1uEo4eNca/a+dL6qYJSd9gaDv/uI+ZjulsA/Eb/QsZAXn+Xq7mdBRMfgQ8DyCRlDmXvrWfaGXY9Ub2aEMxjFtCLcJcSlIzGWhGcpJpOU+CVqHy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=c2fPs86Z; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q9EeZfW8; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="c2fPs86Z"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q9EeZfW8" Date: Tue, 09 Jul 2024 11:41:56 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1720525317; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2/SgvI1wwLrqcJJkWAUEyeidhdbxH9aKtUNOnS64wP8=; b=c2fPs86ZxdvYhddwV87qAcajruHLU8hGgePr1Z/epChxqKPgWdn5+wI7vNVJ0ZCKGKbkH8 vmmAPEaY7UeAQSSfIgpteSjEhyvtJ7GtN0DFbrUrQg1O/JGklBpUhDeFo9ssN25Q54o9OF zbfJ9zYevWZWrWBu+1OrPC/5q1jbs+ywYCnNtYZcLZf9+Kg2ueeS+ZZBMYkEoa4/ihTLVZ 6CtHj+IVG7cCFrW5QYVWCqPEdHN7Xf2BYc5r5LYM8B1VD539bifdKe+Z1kXBWavKuShhbb iUqU4y7W3NO3DyZD+kVsMfXaG1ROgr/1Egv74Nx3AlrO8hlurJb4G4qI/5w/Og== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1720525317; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2/SgvI1wwLrqcJJkWAUEyeidhdbxH9aKtUNOnS64wP8=; b=Q9EeZfW8CqBZylcLYVkjWqZAuLQUo7qd8QLFew3ojYRoBYwdRoWRVahG4jqgGxtCLx+8bn ewiBc756kyfU0hAw== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel/uncore: Fix the bits of the CHA extended umask for SPR Cc: Kan Liang , "Peter Zijlstra (Intel)" , Ian Rogers , stable@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20240708185524.1185505-1-kan.liang@linux.intel.com> References: <20240708185524.1185505-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <172052531679.2215.16140288595428337453.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: a5a6ff3d639d088d4af7e2935e1ee0d8b4e817d4 Gitweb: https://git.kernel.org/tip/a5a6ff3d639d088d4af7e2935e1ee0d8b= 4e817d4 Author: Kan Liang AuthorDate: Mon, 08 Jul 2024 11:55:24 -07:00 Committer: Peter Zijlstra CommitterDate: Tue, 09 Jul 2024 13:26:38 +02:00 perf/x86/intel/uncore: Fix the bits of the CHA extended umask for SPR The perf stat errors out with UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL event. $perf stat -e uncore_cha_55/event=3D0x35,umask=3D0x10c0008101/ -a -- ls event syntax error: '..0x35,umask=3D0x10c0008101/' \___ Bad event or PMU The definition of the CHA umask is config:8-15,32-55, which is 32bit. However, the umask of the event is bigger than 32bit. This is an error in the original uncore spec. Add a new umask_ext5 for the new CHA umask range. Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA= support") Closes: https://lore.kernel.org/linux-perf-users/alpine.LRH.2.20.2401300733= 310.11354@Diego/ Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Ian Rogers Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20240708185524.1185505-1-kan.liang@linux.in= tel.com --- arch/x86/events/intel/uncore_snbep.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index a7ea221..ca98744 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -462,6 +462,7 @@ #define SPR_UBOX_DID 0x3250 =20 /* SPR CHA */ +#define SPR_CHA_EVENT_MASK_EXT 0xffffffff #define SPR_CHA_PMON_CTL_TID_EN (1 << 16) #define SPR_CHA_PMON_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ SPR_CHA_PMON_CTL_TID_EN) @@ -478,6 +479,7 @@ DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-1= 5,32-43,45-55"); DEFINE_UNCORE_FORMAT_ATTR(umask_ext2, umask, "config:8-15,32-57"); DEFINE_UNCORE_FORMAT_ATTR(umask_ext3, umask, "config:8-15,32-39"); DEFINE_UNCORE_FORMAT_ATTR(umask_ext4, umask, "config:8-15,32-55"); +DEFINE_UNCORE_FORMAT_ATTR(umask_ext5, umask, "config:8-15,32-63"); DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16"); DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19"); @@ -5959,7 +5961,7 @@ static struct intel_uncore_ops spr_uncore_chabox_ops = =3D { =20 static struct attribute *spr_uncore_cha_formats_attr[] =3D { &format_attr_event.attr, - &format_attr_umask_ext4.attr, + &format_attr_umask_ext5.attr, &format_attr_tid_en2.attr, &format_attr_edge.attr, &format_attr_inv.attr, @@ -5995,7 +5997,7 @@ ATTRIBUTE_GROUPS(uncore_alias); static struct intel_uncore_type spr_uncore_chabox =3D { .name =3D "cha", .event_mask =3D SPR_CHA_PMON_EVENT_MASK, - .event_mask_ext =3D SPR_RAW_EVENT_MASK_EXT, + .event_mask_ext =3D SPR_CHA_EVENT_MASK_EXT, .num_shared_regs =3D 1, .constraints =3D skx_uncore_chabox_constraints, .ops =3D &spr_uncore_chabox_ops,