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bh=XsjU9LSOLh8kvINVOxc2dJOSFX8ZXHRgq7fIR0zuMcQ=; b=Crsc4/5Er58EB+eHwESeGviDjzAgi9aHbOCwK865XbMKGjjMLJFQr2v1yYDagd4apWyHve np0VU2ickFtWnOB8EvGutxxSFUbzSLwJk7LIFuDt1jWbiFoMY8oBgJOuNP2EHPL7XS3QUO rGo6eEfwE1dJ0Tk7H41Bvim8t89y2fui9fC51yAvn1GE9bAU9m38Jf6mEy6NVGiO37T0hH i9c4QDqSypR2qXUzzLsV23x3S1F5b9Wj88+5CLeyWxAqmtlUZEm2ymgYDHcO+U8p4UDEYJ bta/x9eNjgcp4GhtG7LdgzU9rPr+uhAhpdHuFQjtmEJujUQLO/y9wnki3cOacQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1719165131; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XsjU9LSOLh8kvINVOxc2dJOSFX8ZXHRgq7fIR0zuMcQ=; b=W8zw8y4mVffpGP2lrCe2SlbLvV2tyYXLxPP97ZfjeXueil3F7pwsKTbNS54Tr96xHvCWbG R/HRldzmThlPUWBQ== From: "tip-bot2 for Antonio Borneo" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] irqchip/stm32-exti: Split MCU and MPU code Cc: Antonio Borneo , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20240620083115.204362-5-antonio.borneo@foss.st.com> References: <20240620083115.204362-5-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <171916513146.10875.5808120055008266414.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/core branch of tip: Commit-ID: 350755e2e548ccbe941d045900b57233efa906cb Gitweb: https://git.kernel.org/tip/350755e2e548ccbe941d045900b57233e= fa906cb Author: Antonio Borneo AuthorDate: Thu, 20 Jun 2024 10:31:11 +02:00 Committer: Thomas Gleixner CommitterDate: Sun, 23 Jun 2024 19:49:45 +02:00 irqchip/stm32-exti: Split MCU and MPU code Keep only the code for ARMv7m STM32 MCUs in in stm32-exti.c and split out the code for ARMv7a & ARMv8a STM32MPxxx MPUs into stm32mp-exti.c Signed-off-by: Antonio Borneo Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240620083115.204362-5-antonio.borneo@foss= .st.com --- drivers/irqchip/Kconfig | 3 +- drivers/irqchip/Makefile | 1 +- drivers/irqchip/irq-stm32-exti.c | 670 +------------------------- drivers/irqchip/irq-stm32mp-exti.c | 744 ++++++++++++++++++++++++++++- 4 files changed, 751 insertions(+), 667 deletions(-) create mode 100644 drivers/irqchip/irq-stm32mp-exti.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bc5e191..978639d 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -406,7 +406,8 @@ config PARTITION_PERCPU =20 config STM32MP_EXTI bool - select STM32_EXTI + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP =20 config STM32_EXTI bool diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 1062e71..de091a9 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_MVEBU_SEI) +=3D irq-mvebu-sei.o obj-$(CONFIG_LS_EXTIRQ) +=3D irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) +=3D irq-ls-scfg-msi.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-a= speed-scu-ic.o +obj-$(CONFIG_STM32MP_EXTI) +=3D irq-stm32mp-exti.o obj-$(CONFIG_STM32_EXTI) +=3D irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) +=3D qcom-irq-combiner.o obj-$(CONFIG_IRQ_UNIPHIER_AIDET) +=3D irq-uniphier-aidet.o diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index 2cc9f3b..7c6a008 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -1,45 +1,22 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) Maxime Coquelin 2015 - * Copyright (C) STMicroelectronics 2017 + * Copyright (C) STMicroelectronics 2017-2024 * Author: Maxime Coquelin */ =20 #include -#include -#include #include #include #include #include #include #include -#include -#include #include #include -#include -#include - -#include =20 #define IRQS_PER_BANK 32 =20 -#define HWSPNLCK_TIMEOUT 1000 /* usec */ - -#define EXTI_EnCIDCFGR(n) (0x180 + (n) * 4) -#define EXTI_HWCFGR1 0x3f0 - -/* Register: EXTI_EnCIDCFGR(n) */ -#define EXTI_CIDCFGR_CFEN_MASK BIT(0) -#define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4) -#define EXTI_CIDCFGR_CID_SHIFT 4 - -/* Register: EXTI_HWCFGR1 */ -#define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24) - -#define EXTI_CID1 1 - struct stm32_exti_bank { u32 imr_ofst; u32 emr_ofst; @@ -47,13 +24,8 @@ struct stm32_exti_bank { u32 ftsr_ofst; u32 swier_ofst; u32 rpr_ofst; - u32 fpr_ofst; - u32 trg_ofst; - u32 seccfgr_ofst; }; =20 -#define UNDEF_REG ~0 - struct stm32_exti_drv_data { const struct stm32_exti_bank **exti_banks; const u8 *desc_irqs; @@ -63,7 +35,6 @@ struct stm32_exti_drv_data { struct stm32_exti_chip_data { struct stm32_exti_host_data *host_data; const struct stm32_exti_bank *reg_bank; - struct raw_spinlock rlock; u32 wake_active; u32 mask_cache; u32 rtsr_cache; @@ -76,8 +47,6 @@ struct stm32_exti_host_data { struct device *dev; struct stm32_exti_chip_data *chips_data; const struct stm32_exti_drv_data *drv_data; - struct hwspinlock *hwlock; - bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from D= T */ }; =20 static const struct stm32_exti_bank stm32f4xx_exti_b1 =3D { @@ -87,9 +56,6 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 =3D= { .ftsr_ofst =3D 0x0C, .swier_ofst =3D 0x10, .rpr_ofst =3D 0x14, - .fpr_ofst =3D UNDEF_REG, - .trg_ofst =3D UNDEF_REG, - .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] =3D { @@ -108,9 +74,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 = =3D { .ftsr_ofst =3D 0x04, .swier_ofst =3D 0x08, .rpr_ofst =3D 0x88, - .fpr_ofst =3D UNDEF_REG, - .trg_ofst =3D UNDEF_REG, - .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank stm32h7xx_exti_b2 =3D { @@ -120,9 +83,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = =3D { .ftsr_ofst =3D 0x24, .swier_ofst =3D 0x28, .rpr_ofst =3D 0x98, - .fpr_ofst =3D UNDEF_REG, - .trg_ofst =3D UNDEF_REG, - .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank stm32h7xx_exti_b3 =3D { @@ -132,9 +92,6 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = =3D { .ftsr_ofst =3D 0x44, .swier_ofst =3D 0x48, .rpr_ofst =3D 0xA8, - .fpr_ofst =3D UNDEF_REG, - .trg_ofst =3D UNDEF_REG, - .seccfgr_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] =3D { @@ -148,183 +105,12 @@ static const struct stm32_exti_drv_data stm32h7xx_dr= v_data =3D { .bank_nr =3D ARRAY_SIZE(stm32h7xx_exti_banks), }; =20 -static const struct stm32_exti_bank stm32mp1_exti_b1 =3D { - .imr_ofst =3D 0x80, - .emr_ofst =3D UNDEF_REG, - .rtsr_ofst =3D 0x00, - .ftsr_ofst =3D 0x04, - .swier_ofst =3D 0x08, - .rpr_ofst =3D 0x0C, - .fpr_ofst =3D 0x10, - .trg_ofst =3D 0x3EC, - .seccfgr_ofst =3D 0x14, -}; - -static const struct stm32_exti_bank stm32mp1_exti_b2 =3D { - .imr_ofst =3D 0x90, - .emr_ofst =3D UNDEF_REG, - .rtsr_ofst =3D 0x20, - .ftsr_ofst =3D 0x24, - .swier_ofst =3D 0x28, - .rpr_ofst =3D 0x2C, - .fpr_ofst =3D 0x30, - .trg_ofst =3D 0x3E8, - .seccfgr_ofst =3D 0x34, -}; - -static const struct stm32_exti_bank stm32mp1_exti_b3 =3D { - .imr_ofst =3D 0xA0, - .emr_ofst =3D UNDEF_REG, - .rtsr_ofst =3D 0x40, - .ftsr_ofst =3D 0x44, - .swier_ofst =3D 0x48, - .rpr_ofst =3D 0x4C, - .fpr_ofst =3D 0x50, - .trg_ofst =3D 0x3E4, - .seccfgr_ofst =3D 0x54, -}; - -static const struct stm32_exti_bank *stm32mp1_exti_banks[] =3D { - &stm32mp1_exti_b1, - &stm32mp1_exti_b2, - &stm32mp1_exti_b3, -}; - -static struct irq_chip stm32_exti_h_chip; -static struct irq_chip stm32_exti_h_chip_direct; - -#define EXTI_INVALID_IRQ U8_MAX -#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER= _BANK) - -/* - * Use some intentionally tricky logic here to initialize the whole array = to - * EXTI_INVALID_IRQ, but then override certain fields, requiring us to ind= icate - * that we "know" that there are overrides in this structure, and we'll ne= ed to - * disable that warning from W=3D1 builds. - */ -__diag_push(); -__diag_ignore_all("-Woverride-init", - "logic to initialize all and then override some is OK"); - -static const u8 stm32mp1_desc_irq[] =3D { - /* default value */ - [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] =3D EXTI_INVALID_IRQ, - - [0] =3D 6, - [1] =3D 7, - [2] =3D 8, - [3] =3D 9, - [4] =3D 10, - [5] =3D 23, - [6] =3D 64, - [7] =3D 65, - [8] =3D 66, - [9] =3D 67, - [10] =3D 40, - [11] =3D 42, - [12] =3D 76, - [13] =3D 77, - [14] =3D 121, - [15] =3D 127, - [16] =3D 1, - [19] =3D 3, - [21] =3D 31, - [22] =3D 33, - [23] =3D 72, - [24] =3D 95, - [25] =3D 107, - [26] =3D 37, - [27] =3D 38, - [28] =3D 39, - [29] =3D 71, - [30] =3D 52, - [31] =3D 53, - [32] =3D 82, - [33] =3D 83, - [46] =3D 151, - [47] =3D 93, - [48] =3D 138, - [50] =3D 139, - [52] =3D 140, - [53] =3D 141, - [54] =3D 135, - [61] =3D 100, - [65] =3D 144, - [68] =3D 143, - [70] =3D 62, - [73] =3D 129, -}; - -static const u8 stm32mp13_desc_irq[] =3D { - /* default value */ - [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] =3D EXTI_INVALID_IRQ, - - [0] =3D 6, - [1] =3D 7, - [2] =3D 8, - [3] =3D 9, - [4] =3D 10, - [5] =3D 24, - [6] =3D 65, - [7] =3D 66, - [8] =3D 67, - [9] =3D 68, - [10] =3D 41, - [11] =3D 43, - [12] =3D 77, - [13] =3D 78, - [14] =3D 106, - [15] =3D 109, - [16] =3D 1, - [19] =3D 3, - [21] =3D 32, - [22] =3D 34, - [23] =3D 73, - [24] =3D 93, - [25] =3D 114, - [26] =3D 38, - [27] =3D 39, - [28] =3D 40, - [29] =3D 72, - [30] =3D 53, - [31] =3D 54, - [32] =3D 83, - [33] =3D 84, - [44] =3D 96, - [47] =3D 92, - [48] =3D 116, - [50] =3D 117, - [52] =3D 118, - [53] =3D 119, - [68] =3D 63, - [70] =3D 98, -}; - -__diag_pop(); - -static const struct stm32_exti_drv_data stm32mp1_drv_data =3D { - .exti_banks =3D stm32mp1_exti_banks, - .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), - .desc_irqs =3D stm32mp1_desc_irq, -}; - -static const struct stm32_exti_drv_data stm32mp13_drv_data =3D { - .exti_banks =3D stm32mp1_exti_banks, - .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), - .desc_irqs =3D stm32mp13_desc_irq, -}; - static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) { struct stm32_exti_chip_data *chip_data =3D gc->private; const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; - unsigned long pending; =20 - pending =3D irq_reg_readl(gc, stm32_bank->rpr_ofst); - if (stm32_bank->fpr_ofst !=3D UNDEF_REG) - pending |=3D irq_reg_readl(gc, stm32_bank->fpr_ofst); - - return pending; + return irq_reg_readl(gc, stm32_bank->rpr_ofst); } =20 static void stm32_irq_handler(struct irq_desc *desc) @@ -380,33 +166,21 @@ static int stm32_irq_set_type(struct irq_data *d, uns= igned int type) struct irq_chip_generic *gc =3D irq_data_get_irq_chip_data(d); struct stm32_exti_chip_data *chip_data =3D gc->private; const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; - struct hwspinlock *hwlock =3D chip_data->host_data->hwlock; u32 rtsr, ftsr; int err; =20 irq_gc_lock(gc); =20 - if (hwlock) { - err =3D hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); - if (err) { - pr_err("%s can't get hwspinlock (%d)\n", __func__, err); - goto unlock; - } - } - rtsr =3D irq_reg_readl(gc, stm32_bank->rtsr_ofst); ftsr =3D irq_reg_readl(gc, stm32_bank->ftsr_ofst); =20 err =3D stm32_exti_set_type(d, type, &rtsr, &ftsr); if (err) - goto unspinlock; + goto unlock; =20 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); =20 -unspinlock: - if (hwlock) - hwspin_unlock_in_atomic(hwlock); unlock: irq_gc_unlock(gc); =20 @@ -494,287 +268,10 @@ static void stm32_irq_ack(struct irq_data *d) irq_gc_lock(gc); =20 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); - if (stm32_bank->fpr_ofst !=3D UNDEF_REG) - irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); =20 irq_gc_unlock(gc); } =20 -/* directly set the target bit without reading first. */ -static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - void __iomem *base =3D chip_data->host_data->base; - u32 val =3D BIT(d->hwirq % IRQS_PER_BANK); - - writel_relaxed(val, base + reg); -} - -static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - void __iomem *base =3D chip_data->host_data->base; - u32 val; - - val =3D readl_relaxed(base + reg); - val |=3D BIT(d->hwirq % IRQS_PER_BANK); - writel_relaxed(val, base + reg); - - return val; -} - -static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - void __iomem *base =3D chip_data->host_data->base; - u32 val; - - val =3D readl_relaxed(base + reg); - val &=3D ~BIT(d->hwirq % IRQS_PER_BANK); - writel_relaxed(val, base + reg); - - return val; -} - -static void stm32_exti_h_eoi(struct irq_data *d) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; - - raw_spin_lock(&chip_data->rlock); - - stm32_exti_write_bit(d, stm32_bank->rpr_ofst); - if (stm32_bank->fpr_ofst !=3D UNDEF_REG) - stm32_exti_write_bit(d, stm32_bank->fpr_ofst); - - raw_spin_unlock(&chip_data->rlock); - - if (d->parent_data->chip) - irq_chip_eoi_parent(d); -} - -static void stm32_exti_h_mask(struct irq_data *d) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; - - raw_spin_lock(&chip_data->rlock); - chip_data->mask_cache =3D stm32_exti_clr_bit(d, stm32_bank->imr_ofst); - raw_spin_unlock(&chip_data->rlock); - - if (d->parent_data->chip) - irq_chip_mask_parent(d); -} - -static void stm32_exti_h_unmask(struct irq_data *d) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; - - raw_spin_lock(&chip_data->rlock); - chip_data->mask_cache =3D stm32_exti_set_bit(d, stm32_bank->imr_ofst); - raw_spin_unlock(&chip_data->rlock); - - if (d->parent_data->chip) - irq_chip_unmask_parent(d); -} - -static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; - struct hwspinlock *hwlock =3D chip_data->host_data->hwlock; - void __iomem *base =3D chip_data->host_data->base; - u32 rtsr, ftsr; - int err; - - raw_spin_lock(&chip_data->rlock); - - if (hwlock) { - err =3D hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); - if (err) { - pr_err("%s can't get hwspinlock (%d)\n", __func__, err); - goto unlock; - } - } - - rtsr =3D readl_relaxed(base + stm32_bank->rtsr_ofst); - ftsr =3D readl_relaxed(base + stm32_bank->ftsr_ofst); - - err =3D stm32_exti_set_type(d, type, &rtsr, &ftsr); - if (err) - goto unspinlock; - - writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); - writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); - -unspinlock: - if (hwlock) - hwspin_unlock_in_atomic(hwlock); -unlock: - raw_spin_unlock(&chip_data->rlock); - - return err; -} - -static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - u32 mask =3D BIT(d->hwirq % IRQS_PER_BANK); - - raw_spin_lock(&chip_data->rlock); - - if (on) - chip_data->wake_active |=3D mask; - else - chip_data->wake_active &=3D ~mask; - - raw_spin_unlock(&chip_data->rlock); - - return 0; -} - -static int stm32_exti_h_set_affinity(struct irq_data *d, - const struct cpumask *dest, bool force) -{ - if (d->parent_data->chip) - return irq_chip_set_affinity_parent(d, dest, force); - - return IRQ_SET_MASK_OK_DONE; -} - -static int stm32_exti_h_suspend(struct device *dev) -{ - struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); - struct stm32_exti_chip_data *chip_data; - int i; - - for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { - chip_data =3D &host_data->chips_data[i]; - stm32_chip_suspend(chip_data, chip_data->wake_active); - } - - return 0; -} - -static int stm32_exti_h_resume(struct device *dev) -{ - struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); - struct stm32_exti_chip_data *chip_data; - int i; - - for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { - chip_data =3D &host_data->chips_data[i]; - stm32_chip_resume(chip_data, chip_data->mask_cache); - } - - return 0; -} - -static int stm32_exti_h_retrigger(struct irq_data *d) -{ - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; - void __iomem *base =3D chip_data->host_data->base; - u32 mask =3D BIT(d->hwirq % IRQS_PER_BANK); - - writel_relaxed(mask, base + stm32_bank->swier_ofst); - - return 0; -} - -static struct irq_chip stm32_exti_h_chip =3D { - .name =3D "stm32-exti-h", - .irq_eoi =3D stm32_exti_h_eoi, - .irq_mask =3D stm32_exti_h_mask, - .irq_unmask =3D stm32_exti_h_unmask, - .irq_retrigger =3D stm32_exti_h_retrigger, - .irq_set_type =3D stm32_exti_h_set_type, - .irq_set_wake =3D stm32_exti_h_set_wake, - .flags =3D IRQCHIP_MASK_ON_SUSPEND, - .irq_set_affinity =3D IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity = : NULL, -}; - -static struct irq_chip stm32_exti_h_chip_direct =3D { - .name =3D "stm32-exti-h-direct", - .irq_eoi =3D irq_chip_eoi_parent, - .irq_ack =3D irq_chip_ack_parent, - .irq_mask =3D stm32_exti_h_mask, - .irq_unmask =3D stm32_exti_h_unmask, - .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D irq_chip_set_type_parent, - .irq_set_wake =3D stm32_exti_h_set_wake, - .flags =3D IRQCHIP_MASK_ON_SUSPEND, - .irq_set_affinity =3D IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_pare= nt : NULL, -}; - -static int stm32_exti_h_domain_alloc(struct irq_domain *dm, - unsigned int virq, - unsigned int nr_irqs, void *data) -{ - struct stm32_exti_host_data *host_data =3D dm->host_data; - struct stm32_exti_chip_data *chip_data; - u8 desc_irq; - struct irq_fwspec *fwspec =3D data; - struct irq_fwspec p_fwspec; - irq_hw_number_t hwirq; - int bank; - u32 event_trg; - struct irq_chip *chip; - - hwirq =3D fwspec->param[0]; - if (hwirq >=3D host_data->drv_data->bank_nr * IRQS_PER_BANK) - return -EINVAL; - - bank =3D hwirq / IRQS_PER_BANK; - chip_data =3D &host_data->chips_data[bank]; - - /* Check if event is reserved (Secure) */ - if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) { - dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq); - return -EPERM; - } - - event_trg =3D readl_relaxed(host_data->base + chip_data->reg_bank->trg_of= st); - chip =3D (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? - &stm32_exti_h_chip : &stm32_exti_h_chip_direct; - - irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); - - if (host_data->dt_has_irqs_desc) { - struct of_phandle_args out_irq; - int ret; - - ret =3D of_irq_parse_one(host_data->dev->of_node, hwirq, &out_irq); - if (ret) - return ret; - /* we only support one parent, so far */ - if (of_node_to_fwnode(out_irq.np) !=3D dm->parent->fwnode) - return -EINVAL; - - of_phandle_args_to_fwspec(out_irq.np, out_irq.args, - out_irq.args_count, &p_fwspec); - - return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); - } - - if (!host_data->drv_data->desc_irqs) - return -EINVAL; - - desc_irq =3D host_data->drv_data->desc_irqs[hwirq]; - if (desc_irq !=3D EXTI_INVALID_IRQ) { - p_fwspec.fwnode =3D dm->parent->fwnode; - p_fwspec.param_count =3D 3; - p_fwspec.param[0] =3D GIC_SPI; - p_fwspec.param[1] =3D desc_irq; - p_fwspec.param[2] =3D IRQ_TYPE_LEVEL_HIGH; - - return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); - } - - return 0; -} - static struct stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_dat= a *dd, struct device_node *node) @@ -822,19 +319,12 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm= 32_exti_host_data *h_data, chip_data->host_data =3D h_data; chip_data->reg_bank =3D stm32_bank; =20 - raw_spin_lock_init(&chip_data->rlock); - /* * This IP has no reset, so after hot reboot we should * clear registers to avoid residue */ writel_relaxed(0, base + stm32_bank->imr_ofst); - if (stm32_bank->emr_ofst !=3D UNDEF_REG) - writel_relaxed(0, base + stm32_bank->emr_ofst); - - /* reserve Secure events */ - if (stm32_bank->seccfgr_ofst !=3D UNDEF_REG) - chip_data->event_reserved =3D readl_relaxed(base + stm32_bank->seccfgr_o= fst); + writel_relaxed(0, base + stm32_bank->emr_ofst); =20 pr_info("%pOF: bank%d\n", node, bank_idx); =20 @@ -914,158 +404,6 @@ out_unmap: return ret; } =20 -static const struct irq_domain_ops stm32_exti_h_domain_ops =3D { - .alloc =3D stm32_exti_h_domain_alloc, - .free =3D irq_domain_free_irqs_common, - .xlate =3D irq_domain_xlate_twocell, -}; - -static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data) -{ - unsigned int bank, i, event; - u32 cid, cidcfgr, hwcfgr1; - - /* quit on CID not supported */ - hwcfgr1 =3D readl_relaxed(host_data->base + EXTI_HWCFGR1); - if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) =3D=3D 0) - return; - - for (bank =3D 0; bank < host_data->drv_data->bank_nr; bank++) { - for (i =3D 0; i < IRQS_PER_BANK; i++) { - event =3D bank * IRQS_PER_BANK + i; - cidcfgr =3D readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event)); - cid =3D (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT; - if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid !=3D EXTI_CID1) - host_data->chips_data[bank].event_reserved |=3D BIT(i); - } - } -} - -static void stm32_exti_remove_irq(void *data) -{ - struct irq_domain *domain =3D data; - - irq_domain_remove(domain); -} - -static int stm32_exti_probe(struct platform_device *pdev) -{ - int ret, i; - struct device *dev =3D &pdev->dev; - struct device_node *np =3D dev->of_node; - struct irq_domain *parent_domain, *domain; - struct stm32_exti_host_data *host_data; - const struct stm32_exti_drv_data *drv_data; - - host_data =3D devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); - if (!host_data) - return -ENOMEM; - - dev_set_drvdata(dev, host_data); - host_data->dev =3D dev; - - /* check for optional hwspinlock which may be not available yet */ - ret =3D of_hwspin_lock_get_id(np, 0); - if (ret =3D=3D -EPROBE_DEFER) - /* hwspinlock framework not yet ready */ - return ret; - - if (ret >=3D 0) { - host_data->hwlock =3D devm_hwspin_lock_request_specific(dev, ret); - if (!host_data->hwlock) { - dev_err(dev, "Failed to request hwspinlock\n"); - return -EINVAL; - } - } else if (ret !=3D -ENOENT) { - /* note: ENOENT is a valid case (means 'no hwspinlock') */ - dev_err(dev, "Failed to get hwspinlock\n"); - return ret; - } - - /* initialize host_data */ - drv_data =3D of_device_get_match_data(dev); - if (!drv_data) { - dev_err(dev, "no of match data\n"); - return -ENODEV; - } - host_data->drv_data =3D drv_data; - - host_data->chips_data =3D devm_kcalloc(dev, drv_data->bank_nr, - sizeof(*host_data->chips_data), - GFP_KERNEL); - if (!host_data->chips_data) - return -ENOMEM; - - host_data->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(host_data->base)) - return PTR_ERR(host_data->base); - - for (i =3D 0; i < drv_data->bank_nr; i++) - stm32_exti_chip_init(host_data, i, np); - - stm32_exti_check_rif(host_data); - - parent_domain =3D irq_find_host(of_irq_find_parent(np)); - if (!parent_domain) { - dev_err(dev, "GIC interrupt-parent not found\n"); - return -EINVAL; - } - - domain =3D irq_domain_add_hierarchy(parent_domain, 0, - drv_data->bank_nr * IRQS_PER_BANK, - np, &stm32_exti_h_domain_ops, - host_data); - - if (!domain) { - dev_err(dev, "Could not register exti domain\n"); - return -ENOMEM; - } - - ret =3D devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); - if (ret) - return ret; - - if (of_property_read_bool(np, "interrupts-extended")) - host_data->dt_has_irqs_desc =3D true; - - return 0; -} - -/* platform driver only for MP1 */ -static const struct of_device_id stm32_exti_ids[] =3D { - { .compatible =3D "st,stm32mp1-exti", .data =3D &stm32mp1_drv_data}, - { .compatible =3D "st,stm32mp13-exti", .data =3D &stm32mp13_drv_data}, - {}, -}; -MODULE_DEVICE_TABLE(of, stm32_exti_ids); - -static const struct dev_pm_ops stm32_exti_dev_pm_ops =3D { - NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_exti_h_suspend, stm32_exti_h_resume) -}; - -static struct platform_driver stm32_exti_driver =3D { - .probe =3D stm32_exti_probe, - .driver =3D { - .name =3D "stm32_exti", - .of_match_table =3D stm32_exti_ids, - .pm =3D &stm32_exti_dev_pm_ops, - }, -}; - -static int __init stm32_exti_arch_init(void) -{ - return platform_driver_register(&stm32_exti_driver); -} - -static void __exit stm32_exti_arch_exit(void) -{ - return platform_driver_unregister(&stm32_exti_driver); -} - -arch_initcall(stm32_exti_arch_init); -module_exit(stm32_exti_arch_exit); - -/* no platform driver for F4 and H7 */ static int __init stm32f4_exti_of_init(struct device_node *np, struct device_node *parent) { diff --git a/drivers/irqchip/irq-stm32mp-exti.c b/drivers/irqchip/irq-stm32= mp-exti.c new file mode 100644 index 0000000..8a45ece --- /dev/null +++ b/drivers/irqchip/irq-stm32mp-exti.c @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) Maxime Coquelin 2015 + * Copyright (C) STMicroelectronics 2017-2024 + * Author: Maxime Coquelin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define IRQS_PER_BANK 32 + +#define HWSPNLCK_TIMEOUT 1000 /* usec */ + +#define EXTI_EnCIDCFGR(n) (0x180 + (n) * 4) +#define EXTI_HWCFGR1 0x3f0 + +/* Register: EXTI_EnCIDCFGR(n) */ +#define EXTI_CIDCFGR_CFEN_MASK BIT(0) +#define EXTI_CIDCFGR_CID_MASK GENMASK(6, 4) +#define EXTI_CIDCFGR_CID_SHIFT 4 + +/* Register: EXTI_HWCFGR1 */ +#define EXTI_HWCFGR1_CIDWIDTH_MASK GENMASK(27, 24) + +#define EXTI_CID1 1 + +struct stm32_exti_bank { + u32 imr_ofst; + u32 rtsr_ofst; + u32 ftsr_ofst; + u32 swier_ofst; + u32 rpr_ofst; + u32 fpr_ofst; + u32 trg_ofst; + u32 seccfgr_ofst; +}; + +struct stm32_exti_drv_data { + const struct stm32_exti_bank **exti_banks; + const u8 *desc_irqs; + u32 bank_nr; +}; + +struct stm32_exti_chip_data { + struct stm32_exti_host_data *host_data; + const struct stm32_exti_bank *reg_bank; + struct raw_spinlock rlock; + u32 wake_active; + u32 mask_cache; + u32 rtsr_cache; + u32 ftsr_cache; + u32 event_reserved; +}; + +struct stm32_exti_host_data { + void __iomem *base; + struct device *dev; + struct stm32_exti_chip_data *chips_data; + const struct stm32_exti_drv_data *drv_data; + struct hwspinlock *hwlock; + bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from D= T */ +}; + +static const struct stm32_exti_bank stm32mp1_exti_b1 =3D { + .imr_ofst =3D 0x80, + .rtsr_ofst =3D 0x00, + .ftsr_ofst =3D 0x04, + .swier_ofst =3D 0x08, + .rpr_ofst =3D 0x0C, + .fpr_ofst =3D 0x10, + .trg_ofst =3D 0x3EC, + .seccfgr_ofst =3D 0x14, +}; + +static const struct stm32_exti_bank stm32mp1_exti_b2 =3D { + .imr_ofst =3D 0x90, + .rtsr_ofst =3D 0x20, + .ftsr_ofst =3D 0x24, + .swier_ofst =3D 0x28, + .rpr_ofst =3D 0x2C, + .fpr_ofst =3D 0x30, + .trg_ofst =3D 0x3E8, + .seccfgr_ofst =3D 0x34, +}; + +static const struct stm32_exti_bank stm32mp1_exti_b3 =3D { + .imr_ofst =3D 0xA0, + .rtsr_ofst =3D 0x40, + .ftsr_ofst =3D 0x44, + .swier_ofst =3D 0x48, + .rpr_ofst =3D 0x4C, + .fpr_ofst =3D 0x50, + .trg_ofst =3D 0x3E4, + .seccfgr_ofst =3D 0x54, +}; + +static const struct stm32_exti_bank *stm32mp1_exti_banks[] =3D { + &stm32mp1_exti_b1, + &stm32mp1_exti_b2, + &stm32mp1_exti_b3, +}; + +static struct irq_chip stm32_exti_h_chip; +static struct irq_chip stm32_exti_h_chip_direct; + +#define EXTI_INVALID_IRQ U8_MAX +#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER= _BANK) + +/* + * Use some intentionally tricky logic here to initialize the whole array = to + * EXTI_INVALID_IRQ, but then override certain fields, requiring us to ind= icate + * that we "know" that there are overrides in this structure, and we'll ne= ed to + * disable that warning from W=3D1 builds. + */ +__diag_push(); +__diag_ignore_all("-Woverride-init", + "logic to initialize all and then override some is OK"); + +static const u8 stm32mp1_desc_irq[] =3D { + /* default value */ + [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] =3D EXTI_INVALID_IRQ, + + [0] =3D 6, + [1] =3D 7, + [2] =3D 8, + [3] =3D 9, + [4] =3D 10, + [5] =3D 23, + [6] =3D 64, + [7] =3D 65, + [8] =3D 66, + [9] =3D 67, + [10] =3D 40, + [11] =3D 42, + [12] =3D 76, + [13] =3D 77, + [14] =3D 121, + [15] =3D 127, + [16] =3D 1, + [19] =3D 3, + [21] =3D 31, + [22] =3D 33, + [23] =3D 72, + [24] =3D 95, + [25] =3D 107, + [26] =3D 37, + [27] =3D 38, + [28] =3D 39, + [29] =3D 71, + [30] =3D 52, + [31] =3D 53, + [32] =3D 82, + [33] =3D 83, + [46] =3D 151, + [47] =3D 93, + [48] =3D 138, + [50] =3D 139, + [52] =3D 140, + [53] =3D 141, + [54] =3D 135, + [61] =3D 100, + [65] =3D 144, + [68] =3D 143, + [70] =3D 62, + [73] =3D 129, +}; + +static const u8 stm32mp13_desc_irq[] =3D { + /* default value */ + [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] =3D EXTI_INVALID_IRQ, + + [0] =3D 6, + [1] =3D 7, + [2] =3D 8, + [3] =3D 9, + [4] =3D 10, + [5] =3D 24, + [6] =3D 65, + [7] =3D 66, + [8] =3D 67, + [9] =3D 68, + [10] =3D 41, + [11] =3D 43, + [12] =3D 77, + [13] =3D 78, + [14] =3D 106, + [15] =3D 109, + [16] =3D 1, + [19] =3D 3, + [21] =3D 32, + [22] =3D 34, + [23] =3D 73, + [24] =3D 93, + [25] =3D 114, + [26] =3D 38, + [27] =3D 39, + [28] =3D 40, + [29] =3D 72, + [30] =3D 53, + [31] =3D 54, + [32] =3D 83, + [33] =3D 84, + [44] =3D 96, + [47] =3D 92, + [48] =3D 116, + [50] =3D 117, + [52] =3D 118, + [53] =3D 119, + [68] =3D 63, + [70] =3D 98, +}; + +__diag_pop(); + +static const struct stm32_exti_drv_data stm32mp1_drv_data =3D { + .exti_banks =3D stm32mp1_exti_banks, + .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), + .desc_irqs =3D stm32mp1_desc_irq, +}; + +static const struct stm32_exti_drv_data stm32mp13_drv_data =3D { + .exti_banks =3D stm32mp1_exti_banks, + .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), + .desc_irqs =3D stm32mp13_desc_irq, +}; + +static int stm32_exti_set_type(struct irq_data *d, + unsigned int type, u32 *rtsr, u32 *ftsr) +{ + u32 mask =3D BIT(d->hwirq % IRQS_PER_BANK); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + *rtsr |=3D mask; + *ftsr &=3D ~mask; + break; + case IRQ_TYPE_EDGE_FALLING: + *rtsr &=3D ~mask; + *ftsr |=3D mask; + break; + case IRQ_TYPE_EDGE_BOTH: + *rtsr |=3D mask; + *ftsr |=3D mask; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, + u32 wake_active) +{ + const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + void __iomem *base =3D chip_data->host_data->base; + + /* save rtsr, ftsr registers */ + chip_data->rtsr_cache =3D readl_relaxed(base + stm32_bank->rtsr_ofst); + chip_data->ftsr_cache =3D readl_relaxed(base + stm32_bank->ftsr_ofst); + + writel_relaxed(wake_active, base + stm32_bank->imr_ofst); +} + +static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, + u32 mask_cache) +{ + const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + void __iomem *base =3D chip_data->host_data->base; + + /* restore rtsr, ftsr, registers */ + writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); + writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); + + writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); +} + +/* directly set the target bit without reading first. */ +static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + void __iomem *base =3D chip_data->host_data->base; + u32 val =3D BIT(d->hwirq % IRQS_PER_BANK); + + writel_relaxed(val, base + reg); +} + +static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + void __iomem *base =3D chip_data->host_data->base; + u32 val; + + val =3D readl_relaxed(base + reg); + val |=3D BIT(d->hwirq % IRQS_PER_BANK); + writel_relaxed(val, base + reg); + + return val; +} + +static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + void __iomem *base =3D chip_data->host_data->base; + u32 val; + + val =3D readl_relaxed(base + reg); + val &=3D ~BIT(d->hwirq % IRQS_PER_BANK); + writel_relaxed(val, base + reg); + + return val; +} + +static void stm32_exti_h_eoi(struct irq_data *d) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + + raw_spin_lock(&chip_data->rlock); + + stm32_exti_write_bit(d, stm32_bank->rpr_ofst); + stm32_exti_write_bit(d, stm32_bank->fpr_ofst); + + raw_spin_unlock(&chip_data->rlock); + + if (d->parent_data->chip) + irq_chip_eoi_parent(d); +} + +static void stm32_exti_h_mask(struct irq_data *d) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + + raw_spin_lock(&chip_data->rlock); + chip_data->mask_cache =3D stm32_exti_clr_bit(d, stm32_bank->imr_ofst); + raw_spin_unlock(&chip_data->rlock); + + if (d->parent_data->chip) + irq_chip_mask_parent(d); +} + +static void stm32_exti_h_unmask(struct irq_data *d) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + + raw_spin_lock(&chip_data->rlock); + chip_data->mask_cache =3D stm32_exti_set_bit(d, stm32_bank->imr_ofst); + raw_spin_unlock(&chip_data->rlock); + + if (d->parent_data->chip) + irq_chip_unmask_parent(d); +} + +static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + struct hwspinlock *hwlock =3D chip_data->host_data->hwlock; + void __iomem *base =3D chip_data->host_data->base; + u32 rtsr, ftsr; + int err; + + raw_spin_lock(&chip_data->rlock); + + if (hwlock) { + err =3D hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); + if (err) { + pr_err("%s can't get hwspinlock (%d)\n", __func__, err); + goto unlock; + } + } + + rtsr =3D readl_relaxed(base + stm32_bank->rtsr_ofst); + ftsr =3D readl_relaxed(base + stm32_bank->ftsr_ofst); + + err =3D stm32_exti_set_type(d, type, &rtsr, &ftsr); + if (err) + goto unspinlock; + + writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); + writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); + +unspinlock: + if (hwlock) + hwspin_unlock_in_atomic(hwlock); +unlock: + raw_spin_unlock(&chip_data->rlock); + + return err; +} + +static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + u32 mask =3D BIT(d->hwirq % IRQS_PER_BANK); + + raw_spin_lock(&chip_data->rlock); + + if (on) + chip_data->wake_active |=3D mask; + else + chip_data->wake_active &=3D ~mask; + + raw_spin_unlock(&chip_data->rlock); + + return 0; +} + +static int stm32_exti_h_set_affinity(struct irq_data *d, + const struct cpumask *dest, bool force) +{ + if (d->parent_data->chip) + return irq_chip_set_affinity_parent(d, dest, force); + + return IRQ_SET_MASK_OK_DONE; +} + +static int stm32_exti_h_suspend(struct device *dev) +{ + struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); + struct stm32_exti_chip_data *chip_data; + int i; + + for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { + chip_data =3D &host_data->chips_data[i]; + stm32_chip_suspend(chip_data, chip_data->wake_active); + } + + return 0; +} + +static int stm32_exti_h_resume(struct device *dev) +{ + struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); + struct stm32_exti_chip_data *chip_data; + int i; + + for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { + chip_data =3D &host_data->chips_data[i]; + stm32_chip_resume(chip_data, chip_data->mask_cache); + } + + return 0; +} + +static int stm32_exti_h_retrigger(struct irq_data *d) +{ + struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + void __iomem *base =3D chip_data->host_data->base; + u32 mask =3D BIT(d->hwirq % IRQS_PER_BANK); + + writel_relaxed(mask, base + stm32_bank->swier_ofst); + + return 0; +} + +static struct irq_chip stm32_exti_h_chip =3D { + .name =3D "stm32-exti-h", + .irq_eoi =3D stm32_exti_h_eoi, + .irq_mask =3D stm32_exti_h_mask, + .irq_unmask =3D stm32_exti_h_unmask, + .irq_retrigger =3D stm32_exti_h_retrigger, + .irq_set_type =3D stm32_exti_h_set_type, + .irq_set_wake =3D stm32_exti_h_set_wake, + .flags =3D IRQCHIP_MASK_ON_SUSPEND, + .irq_set_affinity =3D IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity = : NULL, +}; + +static struct irq_chip stm32_exti_h_chip_direct =3D { + .name =3D "stm32-exti-h-direct", + .irq_eoi =3D irq_chip_eoi_parent, + .irq_ack =3D irq_chip_ack_parent, + .irq_mask =3D stm32_exti_h_mask, + .irq_unmask =3D stm32_exti_h_unmask, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_wake =3D stm32_exti_h_set_wake, + .flags =3D IRQCHIP_MASK_ON_SUSPEND, + .irq_set_affinity =3D IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_pare= nt : NULL, +}; + +static int stm32_exti_h_domain_alloc(struct irq_domain *dm, + unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct stm32_exti_host_data *host_data =3D dm->host_data; + struct stm32_exti_chip_data *chip_data; + u8 desc_irq; + struct irq_fwspec *fwspec =3D data; + struct irq_fwspec p_fwspec; + irq_hw_number_t hwirq; + int bank; + u32 event_trg; + struct irq_chip *chip; + + hwirq =3D fwspec->param[0]; + if (hwirq >=3D host_data->drv_data->bank_nr * IRQS_PER_BANK) + return -EINVAL; + + bank =3D hwirq / IRQS_PER_BANK; + chip_data =3D &host_data->chips_data[bank]; + + /* Check if event is reserved (Secure) */ + if (chip_data->event_reserved & BIT(hwirq % IRQS_PER_BANK)) { + dev_err(host_data->dev, "event %lu is reserved, secure\n", hwirq); + return -EPERM; + } + + event_trg =3D readl_relaxed(host_data->base + chip_data->reg_bank->trg_of= st); + chip =3D (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? + &stm32_exti_h_chip : &stm32_exti_h_chip_direct; + + irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); + + if (host_data->dt_has_irqs_desc) { + struct of_phandle_args out_irq; + int ret; + + ret =3D of_irq_parse_one(host_data->dev->of_node, hwirq, &out_irq); + if (ret) + return ret; + /* we only support one parent, so far */ + if (of_node_to_fwnode(out_irq.np) !=3D dm->parent->fwnode) + return -EINVAL; + + of_phandle_args_to_fwspec(out_irq.np, out_irq.args, + out_irq.args_count, &p_fwspec); + + return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); + } + + if (!host_data->drv_data->desc_irqs) + return -EINVAL; + + desc_irq =3D host_data->drv_data->desc_irqs[hwirq]; + if (desc_irq !=3D EXTI_INVALID_IRQ) { + p_fwspec.fwnode =3D dm->parent->fwnode; + p_fwspec.param_count =3D 3; + p_fwspec.param[0] =3D GIC_SPI; + p_fwspec.param[1] =3D desc_irq; + p_fwspec.param[2] =3D IRQ_TYPE_LEVEL_HIGH; + + return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); + } + + return 0; +} + +static struct +stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_= data, + u32 bank_idx, + struct device_node *node) +{ + const struct stm32_exti_bank *stm32_bank; + struct stm32_exti_chip_data *chip_data; + void __iomem *base =3D h_data->base; + + stm32_bank =3D h_data->drv_data->exti_banks[bank_idx]; + chip_data =3D &h_data->chips_data[bank_idx]; + chip_data->host_data =3D h_data; + chip_data->reg_bank =3D stm32_bank; + + raw_spin_lock_init(&chip_data->rlock); + + /* + * This IP has no reset, so after hot reboot we should + * clear registers to avoid residue + */ + writel_relaxed(0, base + stm32_bank->imr_ofst); + + /* reserve Secure events */ + chip_data->event_reserved =3D readl_relaxed(base + stm32_bank->seccfgr_of= st); + + pr_info("%pOF: bank%d\n", node, bank_idx); + + return chip_data; +} + +static const struct irq_domain_ops stm32_exti_h_domain_ops =3D { + .alloc =3D stm32_exti_h_domain_alloc, + .free =3D irq_domain_free_irqs_common, + .xlate =3D irq_domain_xlate_twocell, +}; + +static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data) +{ + unsigned int bank, i, event; + u32 cid, cidcfgr, hwcfgr1; + + /* quit on CID not supported */ + hwcfgr1 =3D readl_relaxed(host_data->base + EXTI_HWCFGR1); + if ((hwcfgr1 & EXTI_HWCFGR1_CIDWIDTH_MASK) =3D=3D 0) + return; + + for (bank =3D 0; bank < host_data->drv_data->bank_nr; bank++) { + for (i =3D 0; i < IRQS_PER_BANK; i++) { + event =3D bank * IRQS_PER_BANK + i; + cidcfgr =3D readl_relaxed(host_data->base + EXTI_EnCIDCFGR(event)); + cid =3D (cidcfgr & EXTI_CIDCFGR_CID_MASK) >> EXTI_CIDCFGR_CID_SHIFT; + if ((cidcfgr & EXTI_CIDCFGR_CFEN_MASK) && cid !=3D EXTI_CID1) + host_data->chips_data[bank].event_reserved |=3D BIT(i); + } + } +} + +static void stm32_exti_remove_irq(void *data) +{ + struct irq_domain *domain =3D data; + + irq_domain_remove(domain); +} + +static int stm32_exti_probe(struct platform_device *pdev) +{ + int ret, i; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct irq_domain *parent_domain, *domain; + struct stm32_exti_host_data *host_data; + const struct stm32_exti_drv_data *drv_data; + + host_data =3D devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); + if (!host_data) + return -ENOMEM; + + dev_set_drvdata(dev, host_data); + host_data->dev =3D dev; + + /* check for optional hwspinlock which may be not available yet */ + ret =3D of_hwspin_lock_get_id(np, 0); + if (ret =3D=3D -EPROBE_DEFER) + /* hwspinlock framework not yet ready */ + return ret; + + if (ret >=3D 0) { + host_data->hwlock =3D devm_hwspin_lock_request_specific(dev, ret); + if (!host_data->hwlock) { + dev_err(dev, "Failed to request hwspinlock\n"); + return -EINVAL; + } + } else if (ret !=3D -ENOENT) { + /* note: ENOENT is a valid case (means 'no hwspinlock') */ + dev_err(dev, "Failed to get hwspinlock\n"); + return ret; + } + + /* initialize host_data */ + drv_data =3D of_device_get_match_data(dev); + if (!drv_data) { + dev_err(dev, "no of match data\n"); + return -ENODEV; + } + host_data->drv_data =3D drv_data; + + host_data->chips_data =3D devm_kcalloc(dev, drv_data->bank_nr, + sizeof(*host_data->chips_data), + GFP_KERNEL); + if (!host_data->chips_data) + return -ENOMEM; + + host_data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(host_data->base)) + return PTR_ERR(host_data->base); + + for (i =3D 0; i < drv_data->bank_nr; i++) + stm32_exti_chip_init(host_data, i, np); + + stm32_exti_check_rif(host_data); + + parent_domain =3D irq_find_host(of_irq_find_parent(np)); + if (!parent_domain) { + dev_err(dev, "GIC interrupt-parent not found\n"); + return -EINVAL; + } + + domain =3D irq_domain_add_hierarchy(parent_domain, 0, + drv_data->bank_nr * IRQS_PER_BANK, + np, &stm32_exti_h_domain_ops, + host_data); + + if (!domain) { + dev_err(dev, "Could not register exti domain\n"); + return -ENOMEM; + } + + ret =3D devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); + if (ret) + return ret; + + if (of_property_read_bool(np, "interrupts-extended")) + host_data->dt_has_irqs_desc =3D true; + + return 0; +} + +static const struct of_device_id stm32_exti_ids[] =3D { + { .compatible =3D "st,stm32mp1-exti", .data =3D &stm32mp1_drv_data}, + { .compatible =3D "st,stm32mp13-exti", .data =3D &stm32mp13_drv_data}, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_exti_ids); + +static const struct dev_pm_ops stm32_exti_dev_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_exti_h_suspend, stm32_exti_h_resume) +}; + +static struct platform_driver stm32_exti_driver =3D { + .probe =3D stm32_exti_probe, + .driver =3D { + .name =3D "stm32_exti", + .of_match_table =3D stm32_exti_ids, + .pm =3D &stm32_exti_dev_pm_ops, + }, +}; + +static int __init stm32_exti_arch_init(void) +{ + return platform_driver_register(&stm32_exti_driver); +} + +static void __exit stm32_exti_arch_exit(void) +{ + return platform_driver_unregister(&stm32_exti_driver); +} + +arch_initcall(stm32_exti_arch_init); +module_exit(stm32_exti_arch_exit);