From nobody Tue Dec 16 13:26:20 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 675401836E6; Sun, 23 Jun 2024 17:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719165135; cv=none; b=PJcNLeLd+NsWZfsk1ZiOspGnHzldTwm9IpCag3Ay7n1pl7HUo9F43zpE9ckq4U2jE6YF9zkCaqjZJC0mdqBSB9H8c0TcQqBulAuWB2EDX6nkT4H17R52LcBJTTDVfaCGAXgCxgsSOH7gdLKQg4w8plfSoP37U2Pwhc6aod7c9TA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719165135; c=relaxed/simple; bh=eDTKFTAXO8mkWwJrCoz4y+x7fqt9THVwbJDzeQMzqHw=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=OkOxlV6fiGAuA+4td0PgNHkfKMttC2X/Y4M2wXeWqQQgfCu4gZA667ir2IOY9beQhDGuZsYtknFF5Vr3fa78DO+wU63uyiiS2Bbibj07i1wUKqpiy7sqWE01mIm/g/3Qj0aZC2K9BN0+P+dkvXjnlbQ5mHjc1MNf50ncitS+hJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bYCShp9O; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=9Lm2o4sx; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bYCShp9O"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="9Lm2o4sx" Date: Sun, 23 Jun 2024 17:52:10 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1719165131; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YUN+8LoVgftE9oY1BJI9dMTeSwUNLR1k/9pyPskTYng=; b=bYCShp9OZDKslrhF35tZNgGfiMzc40rZ44uRSU03NnZYPrvSO5kp4u8Sby8x/zRKLNbrgh F5sRNlbHi4R3FrkziBiFQw9BZELxrEG4dqPXnMAfCsn7Kpt/McGMJc/4inS8rlACdXVyxy /qAQ+F451x4jecEO4CYaLv9g1rnZuxkRJlB5L/1zzxwuNZ9whERWXrdHU1/iY2cXRF2rWo EudbEsq0hWdGkjgEM3EEx6pP0b3LgR/ktUufQXHx7xfveQyjPVARk6gsPJBUuZrvggek1C zC+El6w64N0zA8cUlvinOuDMDjNioSuda52rlIiDXgkQwdfWH/gKzTtJaRIn/Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1719165131; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YUN+8LoVgftE9oY1BJI9dMTeSwUNLR1k/9pyPskTYng=; b=9Lm2o4sxQobeUOPq/Fj/qVBQ89hesivm3lTXQ6gHCD47kW8jcYEFR6d0GwTECb3NNbu4iQ Rd7llcIyeQEBoBBg== From: "tip-bot2 for Antonio Borneo" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] irqchip/stm32mp-exti: Rename internal symbols Cc: Antonio Borneo , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20240620083115.204362-6-antonio.borneo@foss.st.com> References: <20240620083115.204362-6-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <171916513095.10875.5349539394822695701.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/core branch of tip: Commit-ID: c9d269469d2b9a06559cdc84d12dd3fb4d552581 Gitweb: https://git.kernel.org/tip/c9d269469d2b9a06559cdc84d12dd3fb4= d552581 Author: Antonio Borneo AuthorDate: Thu, 20 Jun 2024 10:31:12 +02:00 Committer: Thomas Gleixner CommitterDate: Sun, 23 Jun 2024 19:49:45 +02:00 irqchip/stm32mp-exti: Rename internal symbols Rename all the internal symbols accordingly to the new name of the driver. Renaming done automatically through sed rules: s/stm32_exti_set_type/stm32mp_exti_convert_type/g s/stm32_exti_h_/stm32mp_exti_/g s/stm32_exti/stm32mp_exti/g s/stm32_bank/bank/g s/stm32_/stm32mp_/g s/STM32_/STM32MP_/g s/STM32MP1_/STM32MP_/g s/stm32mp1_exti_/stm32mp_exti_/g s/stm32-exti-h/stm32mp-exti/g Manually fix some indentation after the rename. [ tglx: Mop up more coding style issues while at it ] Signed-off-by: Antonio Borneo Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240620083115.204362-6-antonio.borneo@foss= .st.com --- drivers/irqchip/irq-stm32mp-exti.c | 312 +++++++++++++--------------- 1 file changed, 152 insertions(+), 160 deletions(-) diff --git a/drivers/irqchip/irq-stm32mp-exti.c b/drivers/irqchip/irq-stm32= mp-exti.c index 8a45ece..727859e 100644 --- a/drivers/irqchip/irq-stm32mp-exti.c +++ b/drivers/irqchip/irq-stm32mp-exti.c @@ -38,7 +38,7 @@ =20 #define EXTI_CID1 1 =20 -struct stm32_exti_bank { +struct stm32mp_exti_bank { u32 imr_ofst; u32 rtsr_ofst; u32 ftsr_ofst; @@ -49,33 +49,34 @@ struct stm32_exti_bank { u32 seccfgr_ofst; }; =20 -struct stm32_exti_drv_data { - const struct stm32_exti_bank **exti_banks; - const u8 *desc_irqs; - u32 bank_nr; +struct stm32mp_exti_drv_data { + const struct stm32mp_exti_bank **exti_banks; + const u8 *desc_irqs; + u32 bank_nr; }; =20 -struct stm32_exti_chip_data { - struct stm32_exti_host_data *host_data; - const struct stm32_exti_bank *reg_bank; - struct raw_spinlock rlock; - u32 wake_active; - u32 mask_cache; - u32 rtsr_cache; - u32 ftsr_cache; - u32 event_reserved; +struct stm32mp_exti_chip_data { + struct stm32mp_exti_host_data *host_data; + const struct stm32mp_exti_bank *reg_bank; + struct raw_spinlock rlock; + u32 wake_active; + u32 mask_cache; + u32 rtsr_cache; + u32 ftsr_cache; + u32 event_reserved; }; =20 -struct stm32_exti_host_data { - void __iomem *base; - struct device *dev; - struct stm32_exti_chip_data *chips_data; - const struct stm32_exti_drv_data *drv_data; - struct hwspinlock *hwlock; - bool dt_has_irqs_desc; /* skip internal desc_irqs array and get it from D= T */ +struct stm32mp_exti_host_data { + void __iomem *base; + struct device *dev; + struct stm32mp_exti_chip_data *chips_data; + const struct stm32mp_exti_drv_data *drv_data; + struct hwspinlock *hwlock; + /* skip internal desc_irqs array and get it from DT */ + bool dt_has_irqs_desc; }; =20 -static const struct stm32_exti_bank stm32mp1_exti_b1 =3D { +static const struct stm32mp_exti_bank stm32mp_exti_b1 =3D { .imr_ofst =3D 0x80, .rtsr_ofst =3D 0x00, .ftsr_ofst =3D 0x04, @@ -86,7 +87,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 =3D { .seccfgr_ofst =3D 0x14, }; =20 -static const struct stm32_exti_bank stm32mp1_exti_b2 =3D { +static const struct stm32mp_exti_bank stm32mp_exti_b2 =3D { .imr_ofst =3D 0x90, .rtsr_ofst =3D 0x20, .ftsr_ofst =3D 0x24, @@ -97,7 +98,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 =3D { .seccfgr_ofst =3D 0x34, }; =20 -static const struct stm32_exti_bank stm32mp1_exti_b3 =3D { +static const struct stm32mp_exti_bank stm32mp_exti_b3 =3D { .imr_ofst =3D 0xA0, .rtsr_ofst =3D 0x40, .ftsr_ofst =3D 0x44, @@ -108,17 +109,17 @@ static const struct stm32_exti_bank stm32mp1_exti_b3 = =3D { .seccfgr_ofst =3D 0x54, }; =20 -static const struct stm32_exti_bank *stm32mp1_exti_banks[] =3D { - &stm32mp1_exti_b1, - &stm32mp1_exti_b2, - &stm32mp1_exti_b3, +static const struct stm32mp_exti_bank *stm32mp_exti_banks[] =3D { + &stm32mp_exti_b1, + &stm32mp_exti_b2, + &stm32mp_exti_b3, }; =20 -static struct irq_chip stm32_exti_h_chip; -static struct irq_chip stm32_exti_h_chip_direct; +static struct irq_chip stm32mp_exti_chip; +static struct irq_chip stm32mp_exti_chip_direct; =20 #define EXTI_INVALID_IRQ U8_MAX -#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER= _BANK) +#define STM32MP_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp_exti_banks) * IRQS_PER_= BANK) =20 /* * Use some intentionally tricky logic here to initialize the whole array = to @@ -132,7 +133,7 @@ __diag_ignore_all("-Woverride-init", =20 static const u8 stm32mp1_desc_irq[] =3D { /* default value */ - [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] =3D EXTI_INVALID_IRQ, + [0 ... (STM32MP_DESC_IRQ_SIZE - 1)] =3D EXTI_INVALID_IRQ, =20 [0] =3D 6, [1] =3D 7, @@ -181,7 +182,7 @@ static const u8 stm32mp1_desc_irq[] =3D { =20 static const u8 stm32mp13_desc_irq[] =3D { /* default value */ - [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] =3D EXTI_INVALID_IRQ, + [0 ... (STM32MP_DESC_IRQ_SIZE - 1)] =3D EXTI_INVALID_IRQ, =20 [0] =3D 6, [1] =3D 7, @@ -226,20 +227,19 @@ static const u8 stm32mp13_desc_irq[] =3D { =20 __diag_pop(); =20 -static const struct stm32_exti_drv_data stm32mp1_drv_data =3D { - .exti_banks =3D stm32mp1_exti_banks, - .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), +static const struct stm32mp_exti_drv_data stm32mp1_drv_data =3D { + .exti_banks =3D stm32mp_exti_banks, + .bank_nr =3D ARRAY_SIZE(stm32mp_exti_banks), .desc_irqs =3D stm32mp1_desc_irq, }; =20 -static const struct stm32_exti_drv_data stm32mp13_drv_data =3D { - .exti_banks =3D stm32mp1_exti_banks, - .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), +static const struct stm32mp_exti_drv_data stm32mp13_drv_data =3D { + .exti_banks =3D stm32mp_exti_banks, + .bank_nr =3D ARRAY_SIZE(stm32mp_exti_banks), .desc_irqs =3D stm32mp13_desc_irq, }; =20 -static int stm32_exti_set_type(struct irq_data *d, - unsigned int type, u32 *rtsr, u32 *ftsr) +static int stm32mp_exti_convert_type(struct irq_data *d, unsigned int type= , u32 *rtsr, u32 *ftsr) { u32 mask =3D BIT(d->hwirq % IRQS_PER_BANK); =20 @@ -263,45 +263,43 @@ static int stm32_exti_set_type(struct irq_data *d, return 0; } =20 -static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, - u32 wake_active) +static void stm32mp_chip_suspend(struct stm32mp_exti_chip_data *chip_data,= u32 wake_active) { - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + const struct stm32mp_exti_bank *bank =3D chip_data->reg_bank; void __iomem *base =3D chip_data->host_data->base; =20 /* save rtsr, ftsr registers */ - chip_data->rtsr_cache =3D readl_relaxed(base + stm32_bank->rtsr_ofst); - chip_data->ftsr_cache =3D readl_relaxed(base + stm32_bank->ftsr_ofst); + chip_data->rtsr_cache =3D readl_relaxed(base + bank->rtsr_ofst); + chip_data->ftsr_cache =3D readl_relaxed(base + bank->ftsr_ofst); =20 - writel_relaxed(wake_active, base + stm32_bank->imr_ofst); + writel_relaxed(wake_active, base + bank->imr_ofst); } =20 -static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, - u32 mask_cache) +static void stm32mp_chip_resume(struct stm32mp_exti_chip_data *chip_data, = u32 mask_cache) { - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + const struct stm32mp_exti_bank *bank =3D chip_data->reg_bank; void __iomem *base =3D chip_data->host_data->base; =20 /* restore rtsr, ftsr, registers */ - writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); - writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); + writel_relaxed(chip_data->rtsr_cache, base + bank->rtsr_ofst); + writel_relaxed(chip_data->ftsr_cache, base + bank->ftsr_ofst); =20 - writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); + writel_relaxed(mask_cache, base + bank->imr_ofst); } =20 /* directly set the target bit without reading first. */ -static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg) +static inline void stm32mp_exti_write_bit(struct irq_data *d, u32 reg) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); void __iomem *base =3D chip_data->host_data->base; u32 val =3D BIT(d->hwirq % IRQS_PER_BANK); =20 writel_relaxed(val, base + reg); } =20 -static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) +static inline u32 stm32mp_exti_set_bit(struct irq_data *d, u32 reg) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); void __iomem *base =3D chip_data->host_data->base; u32 val; =20 @@ -312,9 +310,9 @@ static inline u32 stm32_exti_set_bit(struct irq_data *d= , u32 reg) return val; } =20 -static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) +static inline u32 stm32mp_exti_clr_bit(struct irq_data *d, u32 reg) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); void __iomem *base =3D chip_data->host_data->base; u32 val; =20 @@ -325,15 +323,15 @@ static inline u32 stm32_exti_clr_bit(struct irq_data = *d, u32 reg) return val; } =20 -static void stm32_exti_h_eoi(struct irq_data *d) +static void stm32mp_exti_eoi(struct irq_data *d) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); + const struct stm32mp_exti_bank *bank =3D chip_data->reg_bank; =20 raw_spin_lock(&chip_data->rlock); =20 - stm32_exti_write_bit(d, stm32_bank->rpr_ofst); - stm32_exti_write_bit(d, stm32_bank->fpr_ofst); + stm32mp_exti_write_bit(d, bank->rpr_ofst); + stm32mp_exti_write_bit(d, bank->fpr_ofst); =20 raw_spin_unlock(&chip_data->rlock); =20 @@ -341,36 +339,36 @@ static void stm32_exti_h_eoi(struct irq_data *d) irq_chip_eoi_parent(d); } =20 -static void stm32_exti_h_mask(struct irq_data *d) +static void stm32mp_exti_mask(struct irq_data *d) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); + const struct stm32mp_exti_bank *bank =3D chip_data->reg_bank; =20 raw_spin_lock(&chip_data->rlock); - chip_data->mask_cache =3D stm32_exti_clr_bit(d, stm32_bank->imr_ofst); + chip_data->mask_cache =3D stm32mp_exti_clr_bit(d, bank->imr_ofst); raw_spin_unlock(&chip_data->rlock); =20 if (d->parent_data->chip) irq_chip_mask_parent(d); } =20 -static void stm32_exti_h_unmask(struct irq_data *d) +static void stm32mp_exti_unmask(struct irq_data *d) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); + const struct stm32mp_exti_bank *bank =3D chip_data->reg_bank; =20 raw_spin_lock(&chip_data->rlock); - chip_data->mask_cache =3D stm32_exti_set_bit(d, stm32_bank->imr_ofst); + chip_data->mask_cache =3D stm32mp_exti_set_bit(d, bank->imr_ofst); raw_spin_unlock(&chip_data->rlock); =20 if (d->parent_data->chip) irq_chip_unmask_parent(d); } =20 -static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) +static int stm32mp_exti_set_type(struct irq_data *d, unsigned int type) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); + const struct stm32mp_exti_bank *bank =3D chip_data->reg_bank; struct hwspinlock *hwlock =3D chip_data->host_data->hwlock; void __iomem *base =3D chip_data->host_data->base; u32 rtsr, ftsr; @@ -386,28 +384,25 @@ static int stm32_exti_h_set_type(struct irq_data *d, = unsigned int type) } } =20 - rtsr =3D readl_relaxed(base + stm32_bank->rtsr_ofst); - ftsr =3D readl_relaxed(base + stm32_bank->ftsr_ofst); + rtsr =3D readl_relaxed(base + bank->rtsr_ofst); + ftsr =3D readl_relaxed(base + bank->ftsr_ofst); =20 - err =3D stm32_exti_set_type(d, type, &rtsr, &ftsr); - if (err) - goto unspinlock; - - writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); - writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); + err =3D stm32mp_exti_convert_type(d, type, &rtsr, &ftsr); + if (!err) { + writel_relaxed(rtsr, base + bank->rtsr_ofst); + writel_relaxed(ftsr, base + bank->ftsr_ofst); + } =20 -unspinlock: if (hwlock) hwspin_unlock_in_atomic(hwlock); unlock: raw_spin_unlock(&chip_data->rlock); - return err; } =20 -static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) +static int stm32mp_exti_set_wake(struct irq_data *d, unsigned int on) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); u32 mask =3D BIT(d->hwirq % IRQS_PER_BANK); =20 raw_spin_lock(&chip_data->rlock); @@ -422,8 +417,7 @@ static int stm32_exti_h_set_wake(struct irq_data *d, un= signed int on) return 0; } =20 -static int stm32_exti_h_set_affinity(struct irq_data *d, - const struct cpumask *dest, bool force) +static int stm32mp_exti_set_affinity(struct irq_data *d, const struct cpum= ask *dest, bool force) { if (d->parent_data->chip) return irq_chip_set_affinity_parent(d, dest, force); @@ -431,84 +425,84 @@ static int stm32_exti_h_set_affinity(struct irq_data = *d, return IRQ_SET_MASK_OK_DONE; } =20 -static int stm32_exti_h_suspend(struct device *dev) +static int stm32mp_exti_suspend(struct device *dev) { - struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); - struct stm32_exti_chip_data *chip_data; + struct stm32mp_exti_host_data *host_data =3D dev_get_drvdata(dev); + struct stm32mp_exti_chip_data *chip_data; int i; =20 for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { chip_data =3D &host_data->chips_data[i]; - stm32_chip_suspend(chip_data, chip_data->wake_active); + stm32mp_chip_suspend(chip_data, chip_data->wake_active); } =20 return 0; } =20 -static int stm32_exti_h_resume(struct device *dev) +static int stm32mp_exti_resume(struct device *dev) { - struct stm32_exti_host_data *host_data =3D dev_get_drvdata(dev); - struct stm32_exti_chip_data *chip_data; + struct stm32mp_exti_host_data *host_data =3D dev_get_drvdata(dev); + struct stm32mp_exti_chip_data *chip_data; int i; =20 for (i =3D 0; i < host_data->drv_data->bank_nr; i++) { chip_data =3D &host_data->chips_data[i]; - stm32_chip_resume(chip_data, chip_data->mask_cache); + stm32mp_chip_resume(chip_data, chip_data->mask_cache); } =20 return 0; } =20 -static int stm32_exti_h_retrigger(struct irq_data *d) +static int stm32mp_exti_retrigger(struct irq_data *d) { - struct stm32_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d); - const struct stm32_exti_bank *stm32_bank =3D chip_data->reg_bank; + struct stm32mp_exti_chip_data *chip_data =3D irq_data_get_irq_chip_data(d= ); + const struct stm32mp_exti_bank *bank =3D chip_data->reg_bank; void __iomem *base =3D chip_data->host_data->base; u32 mask =3D BIT(d->hwirq % IRQS_PER_BANK); =20 - writel_relaxed(mask, base + stm32_bank->swier_ofst); + writel_relaxed(mask, base + bank->swier_ofst); =20 return 0; } =20 -static struct irq_chip stm32_exti_h_chip =3D { - .name =3D "stm32-exti-h", - .irq_eoi =3D stm32_exti_h_eoi, - .irq_mask =3D stm32_exti_h_mask, - .irq_unmask =3D stm32_exti_h_unmask, - .irq_retrigger =3D stm32_exti_h_retrigger, - .irq_set_type =3D stm32_exti_h_set_type, - .irq_set_wake =3D stm32_exti_h_set_wake, +static struct irq_chip stm32mp_exti_chip =3D { + .name =3D "stm32mp-exti", + .irq_eoi =3D stm32mp_exti_eoi, + .irq_mask =3D stm32mp_exti_mask, + .irq_unmask =3D stm32mp_exti_unmask, + .irq_retrigger =3D stm32mp_exti_retrigger, + .irq_set_type =3D stm32mp_exti_set_type, + .irq_set_wake =3D stm32mp_exti_set_wake, .flags =3D IRQCHIP_MASK_ON_SUSPEND, - .irq_set_affinity =3D IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity = : NULL, + .irq_set_affinity =3D IS_ENABLED(CONFIG_SMP) ? stm32mp_exti_set_affinity = : NULL, }; =20 -static struct irq_chip stm32_exti_h_chip_direct =3D { - .name =3D "stm32-exti-h-direct", +static struct irq_chip stm32mp_exti_chip_direct =3D { + .name =3D "stm32mp-exti-direct", .irq_eoi =3D irq_chip_eoi_parent, .irq_ack =3D irq_chip_ack_parent, - .irq_mask =3D stm32_exti_h_mask, - .irq_unmask =3D stm32_exti_h_unmask, + .irq_mask =3D stm32mp_exti_mask, + .irq_unmask =3D stm32mp_exti_unmask, .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_set_type =3D irq_chip_set_type_parent, - .irq_set_wake =3D stm32_exti_h_set_wake, + .irq_set_wake =3D stm32mp_exti_set_wake, .flags =3D IRQCHIP_MASK_ON_SUSPEND, .irq_set_affinity =3D IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_pare= nt : NULL, }; =20 -static int stm32_exti_h_domain_alloc(struct irq_domain *dm, +static int stm32mp_exti_domain_alloc(struct irq_domain *dm, unsigned int virq, unsigned int nr_irqs, void *data) { - struct stm32_exti_host_data *host_data =3D dm->host_data; - struct stm32_exti_chip_data *chip_data; - u8 desc_irq; + struct stm32mp_exti_host_data *host_data =3D dm->host_data; + struct stm32mp_exti_chip_data *chip_data; struct irq_fwspec *fwspec =3D data; struct irq_fwspec p_fwspec; irq_hw_number_t hwirq; - int bank; - u32 event_trg; struct irq_chip *chip; + u32 event_trg; + u8 desc_irq; + int bank; =20 hwirq =3D fwspec->param[0]; if (hwirq >=3D host_data->drv_data->bank_nr * IRQS_PER_BANK) @@ -525,7 +519,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain = *dm, =20 event_trg =3D readl_relaxed(host_data->base + chip_data->reg_bank->trg_of= st); chip =3D (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? - &stm32_exti_h_chip : &stm32_exti_h_chip_direct; + &stm32mp_exti_chip : &stm32mp_exti_chip_direct; =20 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); =20 @@ -563,19 +557,17 @@ static int stm32_exti_h_domain_alloc(struct irq_domai= n *dm, return 0; } =20 -static struct -stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_= data, - u32 bank_idx, - struct device_node *node) +static struct stm32mp_exti_chip_data *stm32mp_exti_chip_init(struct stm32m= p_exti_host_data *h_data, + u32 bank_idx, struct device_node *node) { - const struct stm32_exti_bank *stm32_bank; - struct stm32_exti_chip_data *chip_data; + struct stm32mp_exti_chip_data *chip_data; + const struct stm32mp_exti_bank *bank; void __iomem *base =3D h_data->base; =20 - stm32_bank =3D h_data->drv_data->exti_banks[bank_idx]; + bank =3D h_data->drv_data->exti_banks[bank_idx]; chip_data =3D &h_data->chips_data[bank_idx]; chip_data->host_data =3D h_data; - chip_data->reg_bank =3D stm32_bank; + chip_data->reg_bank =3D bank; =20 raw_spin_lock_init(&chip_data->rlock); =20 @@ -583,23 +575,23 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm= 32_exti_host_data *h_data, * This IP has no reset, so after hot reboot we should * clear registers to avoid residue */ - writel_relaxed(0, base + stm32_bank->imr_ofst); + writel_relaxed(0, base + bank->imr_ofst); =20 /* reserve Secure events */ - chip_data->event_reserved =3D readl_relaxed(base + stm32_bank->seccfgr_of= st); + chip_data->event_reserved =3D readl_relaxed(base + bank->seccfgr_ofst); =20 pr_info("%pOF: bank%d\n", node, bank_idx); =20 return chip_data; } =20 -static const struct irq_domain_ops stm32_exti_h_domain_ops =3D { - .alloc =3D stm32_exti_h_domain_alloc, +static const struct irq_domain_ops stm32mp_exti_domain_ops =3D { + .alloc =3D stm32mp_exti_domain_alloc, .free =3D irq_domain_free_irqs_common, .xlate =3D irq_domain_xlate_twocell, }; =20 -static void stm32_exti_check_rif(struct stm32_exti_host_data *host_data) +static void stm32mp_exti_check_rif(struct stm32mp_exti_host_data *host_dat= a) { unsigned int bank, i, event; u32 cid, cidcfgr, hwcfgr1; @@ -620,21 +612,21 @@ static void stm32_exti_check_rif(struct stm32_exti_ho= st_data *host_data) } } =20 -static void stm32_exti_remove_irq(void *data) +static void stm32mp_exti_remove_irq(void *data) { struct irq_domain *domain =3D data; =20 irq_domain_remove(domain); } =20 -static int stm32_exti_probe(struct platform_device *pdev) +static int stm32mp_exti_probe(struct platform_device *pdev) { - int ret, i; + const struct stm32mp_exti_drv_data *drv_data; + struct irq_domain *parent_domain, *domain; + struct stm32mp_exti_host_data *host_data; struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; - struct irq_domain *parent_domain, *domain; - struct stm32_exti_host_data *host_data; - const struct stm32_exti_drv_data *drv_data; + int ret, i; =20 host_data =3D devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); if (!host_data) @@ -680,9 +672,9 @@ static int stm32_exti_probe(struct platform_device *pde= v) return PTR_ERR(host_data->base); =20 for (i =3D 0; i < drv_data->bank_nr; i++) - stm32_exti_chip_init(host_data, i, np); + stm32mp_exti_chip_init(host_data, i, np); =20 - stm32_exti_check_rif(host_data); + stm32mp_exti_check_rif(host_data); =20 parent_domain =3D irq_find_host(of_irq_find_parent(np)); if (!parent_domain) { @@ -692,7 +684,7 @@ static int stm32_exti_probe(struct platform_device *pde= v) =20 domain =3D irq_domain_add_hierarchy(parent_domain, 0, drv_data->bank_nr * IRQS_PER_BANK, - np, &stm32_exti_h_domain_ops, + np, &stm32mp_exti_domain_ops, host_data); =20 if (!domain) { @@ -700,7 +692,7 @@ static int stm32_exti_probe(struct platform_device *pde= v) return -ENOMEM; } =20 - ret =3D devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); + ret =3D devm_add_action_or_reset(dev, stm32mp_exti_remove_irq, domain); if (ret) return ret; =20 @@ -710,35 +702,35 @@ static int stm32_exti_probe(struct platform_device *p= dev) return 0; } =20 -static const struct of_device_id stm32_exti_ids[] =3D { +static const struct of_device_id stm32mp_exti_ids[] =3D { { .compatible =3D "st,stm32mp1-exti", .data =3D &stm32mp1_drv_data}, { .compatible =3D "st,stm32mp13-exti", .data =3D &stm32mp13_drv_data}, {}, }; -MODULE_DEVICE_TABLE(of, stm32_exti_ids); +MODULE_DEVICE_TABLE(of, stm32mp_exti_ids); =20 -static const struct dev_pm_ops stm32_exti_dev_pm_ops =3D { - NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_exti_h_suspend, stm32_exti_h_resume) +static const struct dev_pm_ops stm32mp_exti_dev_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32mp_exti_suspend, stm32mp_exti_resume) }; =20 -static struct platform_driver stm32_exti_driver =3D { - .probe =3D stm32_exti_probe, +static struct platform_driver stm32mp_exti_driver =3D { + .probe =3D stm32mp_exti_probe, .driver =3D { - .name =3D "stm32_exti", - .of_match_table =3D stm32_exti_ids, - .pm =3D &stm32_exti_dev_pm_ops, + .name =3D "stm32mp_exti", + .of_match_table =3D stm32mp_exti_ids, + .pm =3D &stm32mp_exti_dev_pm_ops, }, }; =20 -static int __init stm32_exti_arch_init(void) +static int __init stm32mp_exti_arch_init(void) { - return platform_driver_register(&stm32_exti_driver); + return platform_driver_register(&stm32mp_exti_driver); } =20 -static void __exit stm32_exti_arch_exit(void) +static void __exit stm32mp_exti_arch_exit(void) { - return platform_driver_unregister(&stm32_exti_driver); + return platform_driver_unregister(&stm32mp_exti_driver); } =20 -arch_initcall(stm32_exti_arch_init); -module_exit(stm32_exti_arch_exit); +arch_initcall(stm32mp_exti_arch_init); +module_exit(stm32mp_exti_arch_exit);