From nobody Thu Feb 12 23:04:46 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E4A118FC63; Wed, 5 Jun 2024 16:59:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717606781; cv=none; b=Ns+YfTLp8OAhHseWMGQIm2f1kPnOBM9I/9uNaVhw6dsLAM5rI/otEAE0cGrbaQ1y/2HaRKYhSqtOn+e6kGQzx6I0g1jUDi1vCA5i0elRHtoywS1r4ro7K8LjmjW906GWrLhEOX0d0AqSoasQK1OH568R+/d+5Ylb/uiXx1o9MZ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717606781; c=relaxed/simple; bh=Vbor/LuyBnxVqR+UeYSzL2aS/Z1CbmtWNHNTiStHnkA=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Vk6KK41mYFkLmPK9EXmoKJTjwMUV4t4SM0o8HhNSsENKvHumMWSWAg+IIzX7WtD87yL25dqZhBQ6leTnBaxAsfckHMA3qpXR4wBCL5HoabCNbIzWno+rzzal/VXUlS9PFZnNwoOSvrMwJiQkNScBbKDOISpLRwzDyKQ9BgpjKaE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CkqeEA12; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=s1V2J4YO; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CkqeEA12"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="s1V2J4YO" Date: Wed, 05 Jun 2024 16:59:37 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1717606778; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d9O+/qWbxwigDngnW5eMMmqopqLGOVbxVRWzcbuZ5Qk=; b=CkqeEA128iFjpME+igHtHhR9JGngS34az0MJrKT2IrTFvGDH3md7PttWqjs5j4Ib8Z5o/L FoXbSX+bbKO1B/FLc9poosV6GVyKmOikgG7noJmaCkUx6DTauHpUXr1UTQyLwv1nh89FAG GTcoOwO5Rs12f3rdk95dN8XDQp0qUoSR54IFfa80I80CB0y6TUhHe7wIbEHUCANIbCHxW5 oZC62fw/ennHyMi/qfGHKm7RJJO006zUYotpt1ljO08W+nzNm3vv8VJf6D8iYv1lgeXOFq sVP53CR7UfOei3l3ANJ0mpwmCu3jVK8BgsC2c9aXujCcFHhfEx5qr4Cil4NgvQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1717606778; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d9O+/qWbxwigDngnW5eMMmqopqLGOVbxVRWzcbuZ5Qk=; b=s1V2J4YOJYn1335sg8BfB/KOGCH9W9AAxuWmwIvweN+Jkod5L9VmwS6zEMz72nvXOtnCjT 0ivWiP9CWxjfjNDg== From: "tip-bot2 for Lad Prabhakar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] irqchip/renesas-rzg2l: Add support for RZ/Five SoC Cc: Lad Prabhakar , Thomas Gleixner , Geert Uytterhoeven , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20240604173710.534132-3-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240604173710.534132-3-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <171760677733.10875.15072022336745033454.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/core branch of tip: Commit-ID: d011c022efe275791897668aa421e2db9f2e6450 Gitweb: https://git.kernel.org/tip/d011c022efe275791897668aa421e2db9= f2e6450 Author: Lad Prabhakar AuthorDate: Tue, 04 Jun 2024 18:37:10 +01:00 Committer: Thomas Gleixner CommitterDate: Wed, 05 Jun 2024 18:56:53 +02:00 irqchip/renesas-rzg2l: Add support for RZ/Five SoC The IX45 block has additional mask registers (NMSK/IMSK/TMSK) compared to the RZ/G2L (family) SoC. A new rzfive_irqc_chip irq_chip is introduced for RZ/Five, where function pointers for irq_[un]mask() and irq_[dis|en]able() handle the ([un]masking of the interrupts. The irq_chip pointer is now passed as an init callback and stored in the priv pointer to differentiate between RZ/G2L and RZ/Five. Signed-off-by: Lad Prabhakar Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240604173710.534132-3-prabhakar.mahadev-l= ad.rj@bp.renesas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 148 ++++++++++++++++++++++++++- 1 file changed, 145 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index f6484bf..861a0e5 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -37,6 +37,8 @@ #define TSSEL_SHIFT(n) (8 * (n)) #define TSSEL_MASK GENMASK(7, 0) #define IRQ_MASK 0x3 +#define IMSK 0x10010 +#define TMSK 0x10020 =20 #define TSSR_OFFSET(n) ((n) % 4) #define TSSR_INDEX(n) ((n) / 4) @@ -69,12 +71,14 @@ struct rzg2l_irqc_reg_cache { /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address + * @irqchip: Pointer to struct irq_chip * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { void __iomem *base; + const struct irq_chip *irqchip; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; @@ -138,6 +142,111 @@ static void rzg2l_irqc_eoi(struct irq_data *d) irq_chip_eoi_parent(d); } =20 +static void rzfive_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 bit =3D BIT(hwirq - IRQC_IRQ_START); + + writel_relaxed(readl_relaxed(priv->base + IMSK) | bit, priv->base + IMSK); +} + +static void rzfive_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 bit =3D BIT(hwirq - IRQC_IRQ_START); + + writel_relaxed(readl_relaxed(priv->base + IMSK) & ~bit, priv->base + IMSK= ); +} + +static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 bit =3D BIT(hwirq - IRQC_TINT_START); + + writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK); +} + +static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 bit =3D BIT(hwirq - IRQC_TINT_START); + + writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); +} + +static void rzfive_irqc_mask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + raw_spin_lock(&priv->lock); + if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) + rzfive_irqc_mask_irq_interrupt(priv, hwirq); + else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + rzfive_irqc_mask_tint_interrupt(priv, hwirq); + raw_spin_unlock(&priv->lock); + irq_chip_mask_parent(d); +} + +static void rzfive_irqc_unmask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + raw_spin_lock(&priv->lock); + if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) + rzfive_irqc_unmask_irq_interrupt(priv, hwirq); + else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + rzfive_irqc_unmask_tint_interrupt(priv, hwirq); + raw_spin_unlock(&priv->lock); + irq_chip_unmask_parent(d); +} + +static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) { + u32 offset =3D hwirq - IRQC_TINT_START; + u32 tssr_offset =3D TSSR_OFFSET(offset); + u8 tssr_index =3D TSSR_INDEX(offset); + u32 reg; + + raw_spin_lock(&priv->lock); + if (enable) + rzfive_irqc_unmask_tint_interrupt(priv, hwirq); + else + rzfive_irqc_mask_tint_interrupt(priv, hwirq); + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + if (enable) + reg |=3D TIEN << TSSEL_SHIFT(tssr_offset); + else + reg &=3D ~(TIEN << TSSEL_SHIFT(tssr_offset)); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + raw_spin_unlock(&priv->lock); + } else { + raw_spin_lock(&priv->lock); + if (enable) + rzfive_irqc_unmask_irq_interrupt(priv, hwirq); + else + rzfive_irqc_mask_irq_interrupt(priv, hwirq); + raw_spin_unlock(&priv->lock); + } +} + +static void rzfive_irqc_irq_disable(struct irq_data *d) +{ + irq_chip_disable_parent(d); + rzfive_tint_irq_endisable(d, false); +} + +static void rzfive_irqc_irq_enable(struct irq_data *d) +{ + rzfive_tint_irq_endisable(d, true); + irq_chip_enable_parent(d); +} + static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { unsigned int hw_irq =3D irqd_to_hwirq(d); @@ -321,7 +430,7 @@ static struct syscore_ops rzg2l_irqc_syscore_ops =3D { .resume =3D rzg2l_irqc_irq_resume, }; =20 -static const struct irq_chip irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_chip =3D { .name =3D "rzg2l-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D irq_chip_mask_parent, @@ -338,6 +447,23 @@ static const struct irq_chip irqc_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 +static const struct irq_chip rzfive_irqc_chip =3D { + .name =3D "rzfive-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D rzfive_irqc_mask, + .irq_unmask =3D rzfive_irqc_unmask, + .irq_disable =3D rzfive_irqc_irq_disable, + .irq_enable =3D rzfive_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { @@ -369,7 +495,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, if (hwirq > (IRQC_NUM_IRQ - 1)) return -EINVAL; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, (void *)(uintptr_t)tint); if (ret) return ret; @@ -401,7 +527,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, return 0; } =20 -static int rzg2l_irqc_init(struct device_node *node, struct device_node *p= arent) +static int rzg2l_irqc_common_init(struct device_node *node, struct device_= node *parent, + const struct irq_chip *irq_chip) { struct irq_domain *irq_domain, *parent_domain; struct platform_device *pdev; @@ -422,6 +549,8 @@ static int rzg2l_irqc_init(struct device_node *node, st= ruct device_node *parent) if (!rzg2l_irqc_data) return -ENOMEM; =20 + rzg2l_irqc_data->irqchip =3D irq_chip; + rzg2l_irqc_data->base =3D devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0,= NULL); if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base); @@ -472,8 +601,21 @@ pm_disable: return ret; } =20 +static int __init rzg2l_irqc_init(struct device_node *node, + struct device_node *parent) +{ + return rzg2l_irqc_common_init(node, parent, &rzg2l_irqc_chip); +} + +static int __init rzfive_irqc_init(struct device_node *node, + struct device_node *parent) +{ + return rzg2l_irqc_common_init(node, parent, &rzfive_irqc_chip); +} + IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) +IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_init) IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) MODULE_AUTHOR("Lad Prabhakar "); MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");