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Mon, 3 Jun 2024 11:14:49 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4069F20067; Mon, 3 Jun 2024 11:14:47 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 308F42004E; Mon, 3 Jun 2024 11:14:45 +0000 (GMT) Received: from [172.17.0.2] (unknown [9.3.101.175]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 3 Jun 2024 11:14:45 +0000 (GMT) Subject: [PATCH 4/6] KVM: PPC: Book3S HV: Add one-reg interface for DEXCR register From: Shivaprasad G Bhat To: kvm@vger.kernel.org, linux-doc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: pbonzini@redhat.com, naveen.n.rao@linux.ibm.com, christophe.leroy@csgroup.eu, corbet@lwn.net, mpe@ellerman.id.au, namhyung@kernel.org, npiggin@gmail.com, pbonzini@redhat.com, sbhat@linux.ibm.com, jniethe5@gmail.com, atrajeev@linux.vnet.ibm.com, linux-kernel@vger.kernel.org Date: Mon, 03 Jun 2024 11:14:44 +0000 Message-ID: <171741327891.6631.10339033341166150910.stgit@linux.ibm.com> In-Reply-To: <171741323521.6631.11242552089199677395.stgit@linux.ibm.com> References: <171741323521.6631.11242552089199677395.stgit@linux.ibm.com> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 879TKBnXgQhaFYIU84f2SOq75_EMCTg_ X-Proofpoint-ORIG-GUID: qxq_pOFfdTbTw6Aa2193Vw_aayTuzrgk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-06-03_07,2024-05-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 mlxlogscore=655 lowpriorityscore=0 phishscore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2406030094 The patch adds a one-reg register identifier which can be used to read and set the DEXCR for the guest during enter/exit with KVM_REG_PPC_DEXCR. The specific SPR KVM API documentation too updated. Signed-off-by: Shivaprasad G Bhat Reviewed-by: Nicholas Piggin --- Documentation/virt/kvm/api.rst | 1 + arch/powerpc/include/uapi/asm/kvm.h | 1 + arch/powerpc/kvm/book3s_hv.c | 6 ++++++ tools/arch/powerpc/include/uapi/asm/kvm.h | 1 + 4 files changed, 9 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index a71d91978d9e..81077c654281 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -2441,6 +2441,7 @@ registers, find a list below: PPC KVM_REG_PPC_PTCR 64 PPC KVM_REG_PPC_DAWR1 64 PPC KVM_REG_PPC_DAWRX1 64 + PPC KVM_REG_PPC_DEXCR 64 PPC KVM_REG_PPC_TM_GPR0 64 ... PPC KVM_REG_PPC_TM_GPR31 64 diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uap= i/asm/kvm.h index 1691297a766a..fcb947f65667 100644 --- a/arch/powerpc/include/uapi/asm/kvm.h +++ b/arch/powerpc/include/uapi/asm/kvm.h @@ -645,6 +645,7 @@ struct kvm_ppc_cpu_char { #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4) #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5) +#define KVM_REG_PPC_DEXCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6) =20 /* Transactional Memory checkpointed state: * This is all GPRs, all VSX regs and a subset of SPRs diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index b576781d58d5..1294c6839d37 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -2349,6 +2349,9 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcp= u, u64 id, case KVM_REG_PPC_DAWRX1: *val =3D get_reg_val(id, kvmppc_get_dawrx1_hv(vcpu)); break; + case KVM_REG_PPC_DEXCR: + *val =3D get_reg_val(id, kvmppc_get_dexcr_hv(vcpu)); + break; case KVM_REG_PPC_CIABR: *val =3D get_reg_val(id, kvmppc_get_ciabr_hv(vcpu)); break; @@ -2592,6 +2595,9 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcp= u, u64 id, case KVM_REG_PPC_DAWRX1: kvmppc_set_dawrx1_hv(vcpu, set_reg_val(id, *val) & ~DAWRX_HYP); break; + case KVM_REG_PPC_DEXCR: + kvmppc_set_dexcr_hv(vcpu, set_reg_val(id, *val)); + break; case KVM_REG_PPC_CIABR: kvmppc_set_ciabr_hv(vcpu, set_reg_val(id, *val)); /* Don't allow setting breakpoints in hypervisor code */ diff --git a/tools/arch/powerpc/include/uapi/asm/kvm.h b/tools/arch/powerpc= /include/uapi/asm/kvm.h index 1691297a766a..fcb947f65667 100644 --- a/tools/arch/powerpc/include/uapi/asm/kvm.h +++ b/tools/arch/powerpc/include/uapi/asm/kvm.h @@ -645,6 +645,7 @@ struct kvm_ppc_cpu_char { #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4) #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5) +#define KVM_REG_PPC_DEXCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6) =20 /* Transactional Memory checkpointed state: * This is all GPRs, all VSX regs and a subset of SPRs