From nobody Fri Dec 19 21:10:08 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF03A16D332; Tue, 28 May 2024 18:05:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716919513; cv=none; b=jtYgSk4Rbj0tA/NsW9gpQSglE7JMFekeSzTdGPy6++AxKgc+Rwd7VtcFXAXtXWij6cXW5Dzse0wt6iCNZol8w8j3qYhWjUOjluYrikc+5nf8d1lMCphR5r9cUkd//tuChxuxILZ4dNuaVqbUDjfEJhnItkE9gz7v0mfHFBObVsA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716919513; c=relaxed/simple; bh=QFNOy8KO58uHSxmWuA5wAj4hCAodWrA4dVzimeOI3Rw=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=lMKEQc6vtsna/OuxLXipbDnUJiYeSxm1RdjCJm4AxPtluMhPQ2kgtV7Hss70lyKker9ZdM1flbCpWnJ0hJpUkZQR+kxzjaaBVJ7G/8zTlqLj09HdUBJZFhiaLYEKlNiFkNvO9rN71EWfxXZvWzWwGhYrLYzy0QOotGbiTQY+6gE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=YE8IS4CA; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=qr4V9Gwk; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="YE8IS4CA"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="qr4V9Gwk" Date: Tue, 28 May 2024 18:05:07 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1716919508; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=xYBV1bgSsZnAKnNQ13DuFoV0wvHIy1EsYAIKjWQ2lBM=; b=YE8IS4CAM3GaCoq0eLQjGAB1a+L7M8iUpVhuehmD0WzDGiaT5MT7I+rG4Ieq0iCvNee8Sx 1bC0zVu6BAqsya/1HKXZUvP28msRWZSAdwYvGeVBGL9HzAihwtuAFsuawjaXGgXwI9ZWqc CYLd7IV4qeXDPcIoVL6lRPB0+IU1/ALAN7CMcFmoH8fJ2q2ZXL0klaWtYGu6CB6XSgnhbf hAiwG5GWuX3gpKOIWtc6g+vWmA3OqAjuMIvrybb5ifoas3OaLGDVhuWNhpbHzElismB13D UF81tKY/sWkPkNiYGPnezWZH1B8imHHJISTXAMHwTT7oC5cBYqgxAPU1ncmQ0g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1716919508; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=xYBV1bgSsZnAKnNQ13DuFoV0wvHIy1EsYAIKjWQ2lBM=; b=qr4V9Gwk6eGVApZlu956JGSohufoJmmO7vOH+r8VuRJsCPvZ9GQHkveXE18H3wY5Ei3RyT 6ow4GYaSBYHFFVBA== From: "tip-bot2 for Tony Luck" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/cpu/intel: Switch to new Intel CPU model defines Cc: Tony Luck , Dave Hansen , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <171691950780.10875.16399673929501657266.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 6568fc18c2f62b4f35092e9680fe39f3500f4767 Gitweb: https://git.kernel.org/tip/6568fc18c2f62b4f35092e9680fe39f35= 00f4767 Author: Tony Luck AuthorDate: Mon, 20 May 2024 15:45:59 -07:00 Committer: Dave Hansen CommitterDate: Tue, 28 May 2024 10:59:02 -07:00 x86/cpu/intel: Switch to new Intel CPU model defines New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Link: https://lore.kernel.org/all/20240520224620.9480-29-tony.luck%40intel.= com --- arch/x86/kernel/cpu/intel.c | 108 +++++++++++++++++------------------ 1 file changed, 53 insertions(+), 55 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 3ef4e01..a813089 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -72,19 +72,19 @@ static bool cpu_model_supports_sld __ro_after_init; */ static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) { - switch (c->x86_model) { - case INTEL_FAM6_CORE_YONAH: - case INTEL_FAM6_CORE2_MEROM: - case INTEL_FAM6_CORE2_MEROM_L: - case INTEL_FAM6_CORE2_PENRYN: - case INTEL_FAM6_CORE2_DUNNINGTON: - case INTEL_FAM6_NEHALEM: - case INTEL_FAM6_NEHALEM_G: - case INTEL_FAM6_NEHALEM_EP: - case INTEL_FAM6_NEHALEM_EX: - case INTEL_FAM6_WESTMERE: - case INTEL_FAM6_WESTMERE_EP: - case INTEL_FAM6_SANDYBRIDGE: + switch (c->x86_vfm) { + case INTEL_CORE_YONAH: + case INTEL_CORE2_MEROM: + case INTEL_CORE2_MEROM_L: + case INTEL_CORE2_PENRYN: + case INTEL_CORE2_DUNNINGTON: + case INTEL_NEHALEM: + case INTEL_NEHALEM_G: + case INTEL_NEHALEM_EP: + case INTEL_NEHALEM_EX: + case INTEL_WESTMERE: + case INTEL_WESTMERE_EP: + case INTEL_SANDYBRIDGE: setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); } } @@ -106,9 +106,9 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *= c) */ if (c->x86 !=3D 6) return; - switch (c->x86_model) { - case INTEL_FAM6_XEON_PHI_KNL: - case INTEL_FAM6_XEON_PHI_KNM: + switch (c->x86_vfm) { + case INTEL_XEON_PHI_KNL: + case INTEL_XEON_PHI_KNM: break; default: return; @@ -134,32 +134,32 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86= *c) * - Release note from 20180108 microcode release */ struct sku_microcode { - u8 model; + u32 vfm; u8 stepping; u32 microcode; }; static const struct sku_microcode spectre_bad_microcodes[] =3D { - { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 }, - { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 }, - { INTEL_FAM6_KABYLAKE, 0x09, 0x80 }, - { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 }, - { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 }, - { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e }, - { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c }, - { INTEL_FAM6_BROADWELL, 0x04, 0x28 }, - { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b }, - { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 }, - { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 }, - { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, - { INTEL_FAM6_HASWELL_L, 0x01, 0x21 }, - { INTEL_FAM6_HASWELL_G, 0x01, 0x18 }, - { INTEL_FAM6_HASWELL, 0x03, 0x23 }, - { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, - { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, - { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, + { INTEL_KABYLAKE, 0x0B, 0x80 }, + { INTEL_KABYLAKE, 0x0A, 0x80 }, + { INTEL_KABYLAKE, 0x09, 0x80 }, + { INTEL_KABYLAKE_L, 0x0A, 0x80 }, + { INTEL_KABYLAKE_L, 0x09, 0x80 }, + { INTEL_SKYLAKE_X, 0x03, 0x0100013e }, + { INTEL_SKYLAKE_X, 0x04, 0x0200003c }, + { INTEL_BROADWELL, 0x04, 0x28 }, + { INTEL_BROADWELL_G, 0x01, 0x1b }, + { INTEL_BROADWELL_D, 0x02, 0x14 }, + { INTEL_BROADWELL_D, 0x03, 0x07000011 }, + { INTEL_BROADWELL_X, 0x01, 0x0b000025 }, + { INTEL_HASWELL_L, 0x01, 0x21 }, + { INTEL_HASWELL_G, 0x01, 0x18 }, + { INTEL_HASWELL, 0x03, 0x23 }, + { INTEL_HASWELL_X, 0x02, 0x3b }, + { INTEL_HASWELL_X, 0x04, 0x10 }, + { INTEL_IVYBRIDGE_X, 0x04, 0x42a }, /* Observed in the wild */ - { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b }, - { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 }, + { INTEL_SANDYBRIDGE_X, 0x06, 0x61b }, + { INTEL_SANDYBRIDGE_X, 0x07, 0x712 }, }; =20 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) @@ -173,11 +173,8 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *= c) if (cpu_has(c, X86_FEATURE_HYPERVISOR)) return false; =20 - if (c->x86 !=3D 6) - return false; - for (i =3D 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { - if (c->x86_model =3D=3D spectre_bad_microcodes[i].model && + if (c->x86_vfm =3D=3D spectre_bad_microcodes[i].vfm && c->x86_stepping =3D=3D spectre_bad_microcodes[i].stepping) return (c->microcode <=3D spectre_bad_microcodes[i].microcode); } @@ -265,7 +262,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) * need the microcode to have already been loaded... so if it is * not, recommend a BIOS update and disable large pages. */ - if (c->x86 =3D=3D 6 && c->x86_model =3D=3D 0x1c && c->x86_stepping <=3D 2= && + if (c->x86_vfm =3D=3D INTEL_ATOM_BONNELL && c->x86_stepping <=3D 2 && c->microcode < 0x20e) { pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"= ); clear_cpu_cap(c, X86_FEATURE_PSE); @@ -298,11 +295,11 @@ static void early_init_intel(struct cpuinfo_x86 *c) =20 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ if (c->x86 =3D=3D 6) { - switch (c->x86_model) { - case INTEL_FAM6_ATOM_SALTWELL_MID: - case INTEL_FAM6_ATOM_SALTWELL_TABLET: - case INTEL_FAM6_ATOM_SILVERMONT_MID: - case INTEL_FAM6_ATOM_AIRMONT_NP: + switch (c->x86_vfm) { + case INTEL_ATOM_SALTWELL_MID: + case INTEL_ATOM_SALTWELL_TABLET: + case INTEL_ATOM_SILVERMONT_MID: + case INTEL_ATOM_AIRMONT_NP: set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); break; default: @@ -346,7 +343,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE * to be modified. */ - if (c->x86 =3D=3D 5 && c->x86_model =3D=3D 9) { + if (c->x86_vfm =3D=3D INTEL_QUARK_X1000) { pr_info("Disabling PGE capability bit\n"); setup_clear_cpu_cap(X86_FEATURE_PGE); } @@ -578,12 +575,13 @@ static void init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_PEBS); } =20 - if (c->x86 =3D=3D 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && - (c->x86_model =3D=3D 29 || c->x86_model =3D=3D 46 || c->x86_model =3D= =3D 47)) + if (boot_cpu_has(X86_FEATURE_CLFLUSH) && + (c->x86_vfm =3D=3D INTEL_CORE2_DUNNINGTON || + c->x86_vfm =3D=3D INTEL_NEHALEM_EX || + c->x86_vfm =3D=3D INTEL_WESTMERE_EX)) set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); =20 - if (c->x86 =3D=3D 6 && boot_cpu_has(X86_FEATURE_MWAIT) && - ((c->x86_model =3D=3D INTEL_FAM6_ATOM_GOLDMONT))) + if (boot_cpu_has(X86_FEATURE_MWAIT) && c->x86_vfm =3D=3D INTEL_ATOM_GOLDM= ONT) set_cpu_bug(c, X86_BUG_MONITOR); =20 #ifdef CONFIG_X86_64 @@ -1199,9 +1197,9 @@ void handle_bus_lock(struct pt_regs *regs) * feature even though they do not enumerate IA32_CORE_CAPABILITIES. */ static const struct x86_cpu_id split_lock_cpu_ids[] __initconst =3D { - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0), - X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0), + X86_MATCH_VFM(INTEL_ICELAKE_X, 0), + X86_MATCH_VFM(INTEL_ICELAKE_L, 0), + X86_MATCH_VFM(INTEL_ICELAKE_D, 0), {} };