From nobody Fri Dec 19 20:54:08 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CECDA16C866; Tue, 28 May 2024 18:05:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716919513; cv=none; b=FGScA3nMntmIhaoqfZWdhR9fJjF3+/dEp2xdLThbRNUYyn7r1FAxXn8nI51q1TCKAwPq1CKmTO2TGVj1O0g4M3hK4fBC2KCLYHXsvLm2St3tFuM4CeTtkrEpEtmNooJb/EdaPR8Bh1mRqo4KQiJEnWzd2PL82aVpDghV5nM7kgA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716919513; c=relaxed/simple; bh=5G7tKmfCtHyv18bLVIF0v2xAiIAwF4cOtKBeuU72N98=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=j8+3d38PFyCJ2GKZY/59TBjeYgKubqeazifrggLHBeBPjk1oZYMu6y6JGEh01RfNgJpb267KjFi/ssgtj7wstvsexfUafvGzG9n4TgbKnIp8cbul8jSgwCgsyZE+5+QlublI2xr5HmySO4BSAQ+3bpX+N+E67s8BO+1tdGZ7A1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=vn8Ocd/o; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OBoWAG3U; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="vn8Ocd/o"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OBoWAG3U" Date: Tue, 28 May 2024 18:05:07 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1716919507; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=uYHZBPzRKOs4EVB1O7xnTk06IscfJLUuTsg1am8cADU=; b=vn8Ocd/oT+QrMr6V13OV7bnwkfyWHmsfWu5DKmj6YaWeBDxABTrVHK0vQuQcQNlIPZoPgs wFAaUBii9JYz4RiIxPwu+46Sm2nNh847c70qbQaPEnTCwKwPNPevLLY/24y+M7H5IKVtRd Sdw3EB2w+WjQFbXeQz6fjyToZHa9aMeBDXhG8Zofo1RvDXXOshGuj5NmsB7jwtYIHr//jy CyZT7iAVjYU5EjjKjXoxA2UhSCXc/KcOIIX8iy/2lPJwsqiedVeQtQ5IuVhiFDPvAOYf6Z YutDCmjonb13SSkKWjMzoTzgb4/3uilMp2TtnCn2FaPOrUx71Di4MdGBV7P4MQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1716919507; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=uYHZBPzRKOs4EVB1O7xnTk06IscfJLUuTsg1am8cADU=; b=OBoWAG3UaOfGrC135/xSKrpB06IDAVMlbzGA2LipF/h63NHd3ZjUcsjc8kRSexPMDOMOa6 j+NuZjOCjM3nNzDg== From: "tip-bot2 for Tony Luck" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/PCI: Switch to new Intel CPU model defines Cc: Tony Luck , Dave Hansen , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <171691950764.10875.4006879439642445283.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: ac6bee4bf73cdfbd2234125d387b1db3a5bbfc19 Gitweb: https://git.kernel.org/tip/ac6bee4bf73cdfbd2234125d387b1db3a= 5bbfc19 Author: Tony Luck AuthorDate: Mon, 20 May 2024 15:46:00 -07:00 Committer: Dave Hansen CommitterDate: Tue, 28 May 2024 10:59:02 -07:00 x86/PCI: Switch to new Intel CPU model defines New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Link: https://lore.kernel.org/all/20240520224620.9480-30-tony.luck%40intel.= com --- arch/x86/pci/intel_mid_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 8edd622..933ff79 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -216,7 +216,7 @@ static int pci_write(struct pci_bus *bus, unsigned int = devfn, int where, } =20 static const struct x86_cpu_id intel_mid_cpu_ids[] =3D { - X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL), + X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, NULL), {} }; =20 @@ -243,7 +243,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) model =3D id->model; =20 switch (model) { - case INTEL_FAM6_ATOM_SILVERMONT_MID: + case VFM_MODEL(INTEL_ATOM_SILVERMONT_MID): polarity_low =3D false; =20 /* Special treatment for IRQ0 */