From nobody Fri Dec 19 09:36:09 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E54225750; Mon, 29 Apr 2024 09:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714381325; cv=none; b=QQoWeIuwBl4L0MMoo/yER9Q919QMxxPaq0V5asA8vb/aCiC54/SwYDcLGbDKo1tmvQcSwcmA6iHUfXWZ3JIlZtzMPc9ArN7kpXl8zOzVat8d+WvUGQqwZke66Q4L4hs6KKkcU1oFN+oUz0bsSlfLeHXAz7bxGbTpTWWi3l+dCYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714381325; c=relaxed/simple; bh=I/lUS3ILvzQeKH/WKcIv3q5Y/VKs4bYf1oNhmDJDBvM=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=OHh5klI4n2/O9/ftQRaZ+HP4ZG7l0GYed6T7nUm2r9hpaB73f+HgMvPIgbtBIcPAZJM/KtEfK4g1LI8ndjhkXyzpzAIheDJuh3WctPSsXJx8a+52vtN2ixu3DE3ydrQ8fCvnOHlof20nnyH0fnYd3iOL7JTGP5HsOG7b+NYXJJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3apCYB1m; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CTLgqw/a; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3apCYB1m"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CTLgqw/a" Date: Mon, 29 Apr 2024 09:01:54 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1714381314; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=dxmqiJY3dxPmmf73vWJWQhlFW14yQvGIrlB1SIjmOCY=; b=3apCYB1mDTlDNcNJHm1VMx+roiF+SLHXz1y12PrAox9M3sE0O6joHHDo9P3/zyPvtJUJ4a KMXLoYRiqV7RnxT3j0bKxd3Nx7P89g1wHrWmrsheg9MWYFP7RBD4FolGQ86JZrgcUxyjxK ZBMqnNpZ54d4GYekrUZis0gAt7C+j5mphHuWA0y/Mo5ZUmQ+Yq4PQ0gIFpdKQ33H5d4rMt aOx2zVsbtKAlFutqh2d7kL5idjnSk6a6vuB3QbCMy/YruDZforcqL5jDPr6F17B7BBdG2N tRQFFoPfR6zRbEVMX+dsig41RoxtHEDmpFuieDlmNok0//CUNL4yaOPm9yQFGQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1714381314; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=dxmqiJY3dxPmmf73vWJWQhlFW14yQvGIrlB1SIjmOCY=; b=CTLgqw/a0xxffYAtj/l7AZXcWrxlP+k6amW9w5P2ZQ0O5JZ2Q4XSdgqwIolYerqGrdQUSf tsMKXoo4DNvScODg== From: "tip-bot2 for Tony Luck" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/mce: Switch to new Intel CPU model defines Cc: Tony Luck , Dave Hansen , "Borislav Petkov (AMD)" , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <171438131454.10875.5005390647985843961.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 4a5f2dd162fd68f588784eb9b0a927e3b328736d Gitweb: https://git.kernel.org/tip/4a5f2dd162fd68f588784eb9b0a927e3b= 328736d Author: Tony Luck AuthorDate: Wed, 24 Apr 2024 11:15:11 -07:00 Committer: Borislav Petkov (AMD) CommitterDate: Mon, 29 Apr 2024 10:31:23 +02:00 x86/mce: Switch to new Intel CPU model defines New CPU #defines encode vendor and family as well as model. [ bp: Squash *three* mce patches into one, fold in fix: https://lore.kernel.org/r/20240429022051.63360-1-tony.luck@intel.com ] Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/all/20240424181511.41772-1-tony.luck%40intel.= com --- arch/x86/kernel/cpu/mce/core.c | 6 +++--- arch/x86/kernel/cpu/mce/intel.c | 21 ++++++++++----------- arch/x86/kernel/cpu/mce/severity.c | 10 +++++----- 3 files changed, 18 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 771a9f1..ad0623b 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -47,7 +47,7 @@ #include =20 #include -#include +#include #include #include #include @@ -1948,14 +1948,14 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo= _x86 *c) if (c->x86 =3D=3D 6 && c->x86_model <=3D 13 && cfg->bootlog < 0) cfg->bootlog =3D 0; =20 - if (c->x86 =3D=3D 6 && c->x86_model =3D=3D 45) + if (c->x86_vfm =3D=3D INTEL_SANDYBRIDGE_X) mce_flags.snb_ifu_quirk =3D 1; =20 /* * Skylake, Cascacde Lake and Cooper Lake require a quirk on * rep movs. */ - if (c->x86 =3D=3D 6 && c->x86_model =3D=3D INTEL_FAM6_SKYLAKE_X) + if (c->x86_vfm =3D=3D INTEL_SKYLAKE_X) mce_flags.skx_repmov_quirk =3D 1; } =20 diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index 399b62e..f6103e6 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -455,10 +455,10 @@ static void intel_imc_init(struct cpuinfo_x86 *c) { u64 error_control; =20 - switch (c->x86_model) { - case INTEL_FAM6_SANDYBRIDGE_X: - case INTEL_FAM6_IVYBRIDGE_X: - case INTEL_FAM6_HASWELL_X: + switch (c->x86_vfm) { + case INTEL_SANDYBRIDGE_X: + case INTEL_IVYBRIDGE_X: + case INTEL_HASWELL_X: if (rdmsrl_safe(MSR_ERROR_CONTROL, &error_control)) return; error_control |=3D 2; @@ -484,12 +484,11 @@ bool intel_filter_mce(struct mce *m) struct cpuinfo_x86 *c =3D &boot_cpu_data; =20 /* MCE errata HSD131, HSM142, HSW131, BDM48, HSM142 and SKX37 */ - if ((c->x86 =3D=3D 6) && - ((c->x86_model =3D=3D INTEL_FAM6_HASWELL) || - (c->x86_model =3D=3D INTEL_FAM6_HASWELL_L) || - (c->x86_model =3D=3D INTEL_FAM6_BROADWELL) || - (c->x86_model =3D=3D INTEL_FAM6_HASWELL_G) || - (c->x86_model =3D=3D INTEL_FAM6_SKYLAKE_X)) && + if ((c->x86_vfm =3D=3D INTEL_HASWELL || + c->x86_vfm =3D=3D INTEL_HASWELL_L || + c->x86_vfm =3D=3D INTEL_BROADWELL || + c->x86_vfm =3D=3D INTEL_HASWELL_G || + c->x86_vfm =3D=3D INTEL_SKYLAKE_X) && (m->bank =3D=3D 0) && ((m->status & 0xa0000000ffffffff) =3D=3D 0x80000000000f0005)) return true; diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/s= everity.c index fc8988c..e7892f1 100644 --- a/arch/x86/kernel/cpu/mce/severity.c +++ b/arch/x86/kernel/cpu/mce/severity.c @@ -12,7 +12,7 @@ #include =20 #include -#include +#include #include #include #include @@ -45,14 +45,14 @@ static struct severity { unsigned char context; unsigned char excp; unsigned char covered; - unsigned char cpu_model; + unsigned int cpu_vfm; unsigned char cpu_minstepping; unsigned char bank_lo, bank_hi; char *msg; } severities[] =3D { #define MCESEV(s, m, c...) { .sev =3D MCE_ ## s ## _SEVERITY, .msg =3D m, = ## c } #define BANK_RANGE(l, h) .bank_lo =3D l, .bank_hi =3D h -#define MODEL_STEPPING(m, s) .cpu_model =3D m, .cpu_minstepping =3D s +#define VFM_STEPPING(m, s) .cpu_vfm =3D m, .cpu_minstepping =3D s #define KERNEL .context =3D IN_KERNEL #define USER .context =3D IN_USER #define KERNEL_RECOV .context =3D IN_KERNEL_RECOV @@ -128,7 +128,7 @@ static struct severity { MCESEV( AO, "Uncorrected Patrol Scrub Error", SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0), - MODEL_STEPPING(INTEL_FAM6_SKYLAKE_X, 4), BANK_RANGE(13, 18) + VFM_STEPPING(INTEL_SKYLAKE_X, 4), BANK_RANGE(13, 18) ), =20 /* ignore OVER for UCNA */ @@ -398,7 +398,7 @@ static noinstr int mce_severity_intel(struct mce *m, st= ruct pt_regs *regs, char=20 continue; if (s->excp && excp !=3D s->excp) continue; - if (s->cpu_model && boot_cpu_data.x86_model !=3D s->cpu_model) + if (s->cpu_vfm && boot_cpu_data.x86_vfm !=3D s->cpu_vfm) continue; if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minsteppin= g) continue;