From nobody Fri Dec 19 15:43:45 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 250CF14D710; Thu, 25 Apr 2024 17:10:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714065042; cv=none; b=uYHlaNBMKogO+hR3zc5hiTHWgdRYY3C5f/DazR0Z8NVCSUNX8qRZb3N/ogrtr/clr9Wt/GQltaNBMYIARYEg2+FJQfsNA1rd/ONzlZ5HVBAX8E1AdKR6uiOwltBZDHFG5xpGBqAhMMbXYtt+zd4u3pZ0IpHY6YhDV7AayUX8VNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714065042; c=relaxed/simple; bh=ByMaz/QJsYPNvii6+GdcPTurFSFN/T1hJQ//Gnb5aps=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=X9Bu97f6DkfNyTVusoN8X1X3SLsWLiO9/AXlFRwXvWKKSUgfEcGLEVzYcf8OsPLxnxJwPdPz7D+/tgziYWOXYf9Pv1Nu6w2ijAGj3qkXwsuUE6cQy+HEdgg5ijqr5xZDChzEAd4Pd1cgMTFG2FeX6YRcybxTtiCMOL9t2wiYVIQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=I7Xro13e; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0yKx/JnA; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="I7Xro13e"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0yKx/JnA" Date: Thu, 25 Apr 2024 17:10:36 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1714065036; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=cYQIpV2fiGQOl9lqZ/SN1dK7IjYe48S/WU8NznZb1EM=; b=I7Xro13eVWdh3riG1ofBP5/L3j96pbzu9uW6hTONFV89knVjbVKd7fBfatSDhywiviIqWn Tll/S4SHPDi6BdcofQcj/fhnBX8jb1vDvgHd6ypd+JjL4RsK0V0K8Slwre5dmVEB4bM7sa nyzK1nII1AVC+S/BQ2ZO56mmmnjAYflInkGIqns861PWjODL9d1G6c+tvdsamfp39vo+C8 IiJRRoMFDn1JACsNfqHG2F1JICS0EMdNNE5N1U2rx/OoqqAXAc0B5Ec+ehaC5y8TcapTDl 9oOQjRbT6SoJQI0xCArq8nYFbl72ESgaORYJ4RnEukatyFCICiZmSVuKzTte8Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1714065036; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=cYQIpV2fiGQOl9lqZ/SN1dK7IjYe48S/WU8NznZb1EM=; b=0yKx/JnAqSmf67/WRyv0wWSIQxVBaJsrRlTDtXIudZjwTRi0h8mY3ed5lSAYUHZAWiT/sL Bl1vIfBPEscKJBAA== From: "tip-bot2 for Tony Luck" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] perf/x86/intel/uncore: Switch to new Intel CPU model defines Cc: Tony Luck , Dave Hansen , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <171406503644.10875.15432533426136923358.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: d413a1955a8e32e4425ff4dd47f5c6fcf09427c3 Gitweb: https://git.kernel.org/tip/d413a1955a8e32e4425ff4dd47f5c6fcf= 09427c3 Author: Tony Luck AuthorDate: Wed, 24 Apr 2024 11:15:02 -07:00 Committer: Dave Hansen CommitterDate: Thu, 25 Apr 2024 09:04:32 -07:00 perf/x86/intel/uncore: Switch to new Intel CPU model defines New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck Signed-off-by: Dave Hansen Link: https://lore.kernel.org/all/20240424181502.41576-1-tony.luck%40intel.= com --- arch/x86/events/intel/uncore_nhmex.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_nhmex.c b/arch/x86/events/intel/u= ncore_nhmex.c index 92da8aa..4668334 100644 --- a/arch/x86/events/intel/uncore_nhmex.c +++ b/arch/x86/events/intel/uncore_nhmex.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* Nehalem-EX/Westmere-EX uncore support */ +#include #include "uncore.h" =20 /* NHM-EX event control */ @@ -1217,7 +1218,7 @@ static struct intel_uncore_type *nhmex_msr_uncores[] = =3D { =20 void nhmex_uncore_cpu_init(void) { - if (boot_cpu_data.x86_model =3D=3D 46) + if (boot_cpu_data.x86_vfm =3D=3D INTEL_NEHALEM_EX) uncore_nhmex =3D true; else nhmex_uncore_mbox.event_descs =3D wsmex_uncore_mbox_events;