From nobody Tue Feb 10 07:40:38 2026 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 490A11591E5; Wed, 24 Apr 2024 06:39:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713940792; cv=none; b=YuAJ7YV/1DIjGEt9Apwz9wiXi0TiPkY8IiKW0B3OP+zb97g9ZaiGVIIG8w/gfjCGpKtKLFrba0l8vAfbcwD15U3i2bvc3l7RLNYoiLmQxw/fGntWEztu2N0VMW/fGibo+n9QqjTZUdwmo3McsYu/tIUJ1t2hvqTKgP/SjrS0DQU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713940792; c=relaxed/simple; bh=WDpYGlyH3D49ELuXMWqTBaxAX1mUNWhzBM30ioj42AE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=YlhNCaYx3IB3JUFZqwFDHEoTxYSNOEnzquHyODBf7y8bQB8Jgm120lWklETIG8OfUh0JJ75SQIphPqm1oXIdLcgCLOflx3RaIDjVXRR78UTTpOBEu+zjq91czufrA6r5IpWGhBEwOxT/UPe6EFn0U4FaHbcHLBOQn0qaZqwW/94= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 12829202228; Wed, 24 Apr 2024 08:39:44 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 2C6BF201BBB; Wed, 24 Apr 2024 08:39:43 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id BA491181D0FC; Wed, 24 Apr 2024 14:39:40 +0800 (+08) From: Richard Zhu To: conor@kernel.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, frank.li@nxp.com, conor+dt@kernel.org Cc: hongxing.zhu@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v3 1/3] dt-bindings: phy: phy-imx8-pcie: Add header file for i.MX8Q HSIO SerDes PHY Date: Wed, 24 Apr 2024 14:21:21 +0800 Message-Id: <1713939683-15328-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1713939683-15328-1-git-send-email-hongxing.zhu@nxp.com> References: <1713939683-15328-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add lane index and HSIO configuration definitions of the i.MX8Q HSIO SerDes PHY into header file. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- include/dt-bindings/phy/phy-imx8-pcie.h | 62 +++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/= phy/phy-imx8-pcie.h index 8bbe2d6538d8..60447b95a952 100644 --- a/include/dt-bindings/phy/phy-imx8-pcie.h +++ b/include/dt-bindings/phy/phy-imx8-pcie.h @@ -11,4 +11,66 @@ #define IMX8_PCIE_REFCLK_PAD_INPUT 1 #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 =20 +/* + * i.MX8QM HSIO subsystem has three lane PHYs and three controllers: + * PCIEA(2 lanes capable PCIe controller), PCIEB (only support one + * lane) and SATA. + * + * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only + * support one lane) controller. + * + * In the different use cases. PCIEA can be bound to PHY lane0, lane1 + * or Lane0 and lane1. PCIEB can be bound to lane1 or lane2 PHY. SATA + * can only be bound to last lane2 PHY. + * + * +-------------------------------+------------------+ + * | i.MX8QM | i.MX8QXP | + * |-------------------------------|------------------| + * | | PCIEA | PCIEB | SATA | | PCIEB | + * |-------------------------------|-------|----------| + * | LAN 0 | X | | | LAN 0 | * | + * |-------------------------------|-------|----------| + * | LAN 1 | X | * | | | | + * |-------------------------------|-------|----------| + * | LAN 2 | | * | * | | | + * +-------------------------------+------------------+ + * NOTE: + * *: Choose one only. + * X: Choose any of these. + * + * Define i.MX8Q HSIO PHY lane index here to specify the lane mask. + */ +#define IMX8Q_HSIO_LANE0 0x1 +#define IMX8Q_HSIO_LANE1 0x2 +#define IMX8Q_HSIO_LANE2 0x4 + +/* + * Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be + * confiured as following three use cases. + * + * Define different configurations refer to the use cases, since it is + * mandatory required in the initialization. + * + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY. + * Define "IMX8Q_HSIO_CFG_PCIEB" for i.MX8QXP platforms. + * + * +----------------------------------------------------+----------+ + * | | i.MX8QM | i.MX8QXP | + * |-------------------------------|--------------------|----------| + * | | LAN0 | LAN1 | LAN2 | LAN0 | + * |-------------------------------|------|------|------|----------| + * | IMX8Q_HSIO_CFG_PCIEAX2SATA | PCIEA| PCIEA| SATA | | + * |-------------------------------|------|------|------|----------| + * | IMX8Q_HSIO_CFG_PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB| | + * |-------------------------------|------|------|------|----------| + * | IMX8Q_HSIO_CFG_PCIEAPCIEBSATA | PCIEA| PCIEB| SATA | | + * |-------------------------------|------|------|------|----------| + * | IMX8Q_HSIO_CFG_PCIEB | - | - | - | PCIEB | + * +----------------------------------------------------+----------+ + */ +#define IMX8Q_HSIO_CFG_PCIEAX2SATA 0x1 +#define IMX8Q_HSIO_CFG_PCIEAX2PCIEB 0x2 +#define IMX8Q_HSIO_CFG_PCIEAPCIEBSATA (IMX8Q_HSIO_CFG_PCIEAX2SATA | IMX8Q_= HSIO_CFG_PCIEAX2PCIEB) +#define IMX8Q_HSIO_CFG_PCIEB IMX8Q_HSIO_CFG_PCIEAX2PCIEB + #endif /* _DT_BINDINGS_IMX8_PCIE_H */ --=20 2.37.1 From nobody Tue Feb 10 07:40:38 2026 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 073C015956A; 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dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8DCFC1A2312; Wed, 24 Apr 2024 08:39:47 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6F6B91A1E98; Wed, 24 Apr 2024 08:39:44 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 057F2181D0FE; Wed, 24 Apr 2024 14:39:41 +0800 (+08) From: Richard Zhu To: conor@kernel.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, frank.li@nxp.com, conor+dt@kernel.org Cc: hongxing.zhu@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v3 2/3] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding Date: Wed, 24 Apr 2024 14:21:22 +0800 Message-Id: <1713939683-15328-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1713939683-15328-1-git-send-email-hongxing.zhu@nxp.com> References: <1713939683-15328-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at initialization according to board design. Signed-off-by: Richard Zhu --- .../bindings/phy/fsl,imx8qm-hsio.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.y= aml diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml b/D= ocumentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml new file mode 100644 index 000000000000..3e2824d1616c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8QM SoC series HSIO SERDES PHY + +maintainers: + - Richard Zhu + +properties: + compatible: + enum: + - fsl,imx8qm-hsio + - fsl,imx8qxp-hsio + reg: + minItems: 4 + maxItems: 4 + + "#phy-cells": + const: 3 + description: + The first defines the type of the PHY refer to the include phy.h. + The second defines controller index. + The third defines the lane mask of the lane ID, indicated which + lane is used by the PHY. They are defined as HSIO_LAN* in + dt-bindings/phy/phy-imx8-pcie.h + + reg-names: + items: + - const: reg + - const: phy + - const: ctrl + - const: misc + + clocks: + minItems: 5 + maxItems: 14 + + clock-names: + minItems: 5 + maxItems: 14 + + fsl,hsio-cfg: + description: Refer macro HSIO_CFG* include/dt-bindings/phy/phy-imx8-pc= ie.h. + $ref: /schemas/types.yaml#/definitions/uint32 + + fsl,refclk-pad-mode: + description: + Specifies the mode of the refclk pad used. It can be UNUSED(PHY + refclock is derived from SoC internal source), INPUT(PHY refclock + is provided externally via the refclk pad) or OUTPUT(PHY refclock + is derived from SoC internal source and provided on the refclk pad). + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants + to be used. + $ref: /schemas/types.yaml#/definitions/uint32 + default: IMX8_PCIE_REFCLK_PAD_OUTPUT + + power-domains: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - fsl,hsio-cfg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-hsio + then: + properties: + clock-names: + items: + - const: pclk0 + - const: apb_pclk0 + - const: phy0_crr + - const: ctl0_crr + - const: misc_crr + power-domains: + minItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-hsio + then: + properties: + clock-names: + items: + - const: pclk0 + - const: pclk1 + - const: apb_pclk0 + - const: apb_pclk1 + - const: pclk2 + - const: epcs_tx + - const: epcs_rx + - const: apb_pclk2 + - const: phy0_crr + - const: phy1_crr + - const: ctl0_crr + - const: ctl1_crr + - const: ctl2_crr + - const: misc_crr + power-domains: + minItems: 2 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + phy@5f1a0000 { + compatible =3D "fsl,imx8qxp-hsio"; + reg =3D <0x5f1a0000 0x10000>, + <0x5f120000 0x10000>, + <0x5f140000 0x10000>, + <0x5f160000 0x10000>; + reg-names =3D "reg", "phy", "ctrl", "misc"; + clocks =3D <&phyx1_lpcg IMX_LPCG_CLK_0>, + <&phyx1_lpcg IMX_LPCG_CLK_4>, + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; + clock-names =3D "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "mis= c_crr"; + power-domains =3D <&pd IMX_SC_R_SERDES_1>; + #phy-cells =3D <3>; + fsl,hsio-cfg =3D ; + fsl,refclk-pad-mode =3D ; + }; +... --=20 2.37.1 From nobody Tue Feb 10 07:40:38 2026 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6576E1591FE; Wed, 24 Apr 2024 06:39:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713940797; cv=none; b=LRfdCFCWnppa/BW6M4YZ5QpcY6L8axKeomXvrgh1egTKiGwqocL4y1CGAYcP6WfUYCs0v4K1GExPbZExgT96B1Nloz3T07l5vuLDZ7lhUBpjO6vK6PLANjNUj2WSsmpXxZu9yazTIGGmeUFsGJnITwyqH4Q8VrD7H2Q49B2DeW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713940797; c=relaxed/simple; bh=w5Rg5sNuW1Tv21PXx7QR9TLhM1Qb+B49vfOQKudI9mI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=M81gWxTfWma2j9W86G74q8McUEumLCeuTNgAHGZKkc9q7SZwn1tg0kWf1lD/tKaHHZK/bd84rF9vSMgp2NZBiAsqBsxhsccIvUdEcCC4e6ST6D/KXjzfkRsqVevqNtZKBQbrsmP/cyBgany1cSmdhFOX2MGc+NaTZFKKJl8H5QE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2D19E1A22FD; Wed, 24 Apr 2024 08:39:46 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id DF9381A15AA; Wed, 24 Apr 2024 08:39:44 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 47B4B1820F56; Wed, 24 Apr 2024 14:39:43 +0800 (+08) From: Richard Zhu To: conor@kernel.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, frank.li@nxp.com, conor+dt@kernel.org Cc: hongxing.zhu@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v3 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support Date: Wed, 24 Apr 2024 14:21:23 +0800 Message-Id: <1713939683-15328-4-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1713939683-15328-1-git-send-email-hongxing.zhu@nxp.com> References: <1713939683-15328-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add i.MX8QM HSIO PHY driver support. Signed-off-by: Richard Zhu --- drivers/phy/freescale/Kconfig | 8 + drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 607 ++++++++++++++++++++ 3 files changed, 616 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-imx8qm-hsio.c diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 853958fb2c06..c9ee48aeea9e 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -35,6 +35,14 @@ config PHY_FSL_IMX8M_PCIE Enable this to add support for the PCIE PHY as found on i.MX8M family of SOCs. =20 +config PHY_FSL_IMX8QM_HSIO + tristate "Freescale i.MX8QM HSIO PHY" + depends on OF && HAS_IOMEM + select GENERIC_PHY + help + Enable this to add support for the HSIO PHY as found on + i.MX8QM family of SOCs. + endif =20 config PHY_FSL_LYNX_28G diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index cedb328bc4d2..b56b4d5c18ea 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) +=3D phy-fsl-imx8mq-usb.o obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) +=3D phy-fsl-imx8qm-lvds-phy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) +=3D phy-fsl-imx8-mipi-dphy.o obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) +=3D phy-fsl-imx8m-pcie.o +obj-$(CONFIG_PHY_FSL_IMX8QM_HSIO) +=3D phy-fsl-imx8qm-hsio.o obj-$(CONFIG_PHY_FSL_LYNX_28G) +=3D phy-fsl-lynx-28g.o diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/free= scale/phy-fsl-imx8qm-hsio.c new file mode 100644 index 000000000000..b3e17163e859 --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define MAX_NUM_PHY_MIXS 4 +#define PHY_MIX_MAX_NUM_LANES 2 +#define LANE_NUM_CLKS 5 + +/* Parameters for the waiting for PCIe PHY PLL to lock */ +#define PHY_INIT_WAIT_USLEEP_MAX 10 +#define PHY_INIT_WAIT_TIMEOUT (1000 * PHY_INIT_WAIT_USLEEP_MAX) + +/* i.MX8Q HSIO registers */ +#define HSIO_CTRL0 0x0 +#define HSIO_APB_RSTN_0 BIT(0) +#define HSIO_APB_RSTN_1 BIT(1) +#define HSIO_PIPE_RSTN_0_MASK GENMASK(25, 24) +#define HSIO_PIPE_RSTN_1_MASK GENMASK(27, 26) +#define HSIO_MODE_MASK GENMASK(20, 17) +#define HSIO_MODE_PCIE 0x0 +#define HSIO_MODE_SATA 0x4 +#define HSIO_DEVICE_TYPE_MASK GENMASK(27, 24) +#define HSIO_EPCS_TXDEEMP BIT(5) +#define HSIO_EPCS_TXDEEMP_SEL BIT(6) +#define HSIO_EPCS_PHYRESET_N BIT(7) +#define HSIO_RESET_N BIT(12) + +#define HSIO_IOB_RXENA BIT(0) +#define HSIO_IOB_TXENA BIT(1) +#define HSIO_IOB_A_0_TXOE BIT(2) +#define HSIO_IOB_A_0_M1M0_2 BIT(4) +#define HSIO_IOB_A_0_M1M0_MASK GENMASK(4, 3) +#define HSIO_PHYX1_EPCS_SEL BIT(12) +#define HSIO_PCIE_AB_SELECT BIT(13) + +#define HSIO_PHY_STS0 0x4 +#define HSIO_LANE0_TX_PLL_LOCK BIT(4) +#define HSIO_LANE1_TX_PLL_LOCK BIT(12) + +#define HSIO_CTRL2 0x8 +#define HSIO_LTSSM_ENABLE BIT(4) +#define HSIO_BUTTON_RST_N BIT(21) +#define HSIO_PERST_N BIT(22) +#define HSIO_POWER_UP_RST_N BIT(23) + +#define HSIO_PCIE_STS0 0xc +#define HSIO_PM_REQ_CORE_RST BIT(19) + +#define HSIO_REG48_PMA_STATUS 0x30 +#define HSIO_REG48_PMA_RDY BIT(7) + +/* + * There are three lanes PHY in i.MX8QM HSIO, and can be made up the + * following PHY modes in different use cases. + * +------------------------------------+ + * | index | LAN0 | LAN1 | LAN2 | + * |------------------------------------| + * | 0 | PCIEA | | | + * |------------------------------------| + * | 1 | | PCIEB | | + * |------------------------------------| + * | 2 | PCIEA | PCIEA | | + * |------------------------------------| + * | 3 | | | PCIEB/SATA | + * +------------------------------------+ + */ +enum phy_mode_index { + IMX8Q_HSIO_LANE0_PCIE_PHY, + IMX8Q_HSIO_LANE1_PCIE_PHY, + IMX8Q_HSIO_LANE0_1_PCIE_PHY, + IMX8Q_HSIO_LANE2_PHY +}; + +struct imx_hsio_drvdata { + int phy_mix_num; +}; + +struct imx_hsio_phy_lane { + const char * const *clk_names; + struct clk_bulk_data clks[LANE_NUM_CLKS]; +}; + +struct imx_hsio_phy_mix { + u32 ctrl_index; + u32 ctrl_off; + u32 phy_off; + u32 phy_type; + struct imx_hsio_phy_lane lane[PHY_MIX_MAX_NUM_LANES]; + struct imx_hsio_priv *priv; + struct phy *phy; + enum phy_mode pmix_mode; + enum phy_mode_index idx; +}; + +struct imx_hsio_priv { + void __iomem *base; + struct device *dev; + u32 refclk_pad; + u32 hsio_cfg; + struct regmap *phy; + struct regmap *ctrl; + struct regmap *misc; + const struct imx_hsio_drvdata *drvdata; + struct imx_hsio_phy_mix pmix[MAX_NUM_PHY_MIXS]; +}; + +static const char * const lan0_pcie_clks[] =3D {"apb_pclk0", "pclk0", "ctl= 0_crr", + "phy0_crr", "misc_crr"}; +static const char * const lan1_pciea_clks[] =3D {"apb_pclk1", "pclk1", "ct= l0_crr", + "phy0_crr", "misc_crr"}; +static const char * const lan1_pcieb_clks[] =3D {"apb_pclk1", "pclk1", "ct= l1_crr", + "phy0_crr", "misc_crr"}; +static const char * const lan2_pcieb_clks[] =3D {"apb_pclk2", "pclk2", "ct= l1_crr", + "phy1_crr", "misc_crr"}; +static const char * const lan2_sata_clks[] =3D {"pclk2", "epcs_tx", "epcs_= rx", + "phy1_crr", "misc_crr"}; + +static const struct regmap_config regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int imx_hsio_get_idx(int phy_type, int ctrl_index, int lane_mask) +{ + int index; + + switch (phy_type) { + case PHY_TYPE_PCIE: + if (ctrl_index) { /* PCIEB */ + if (lane_mask =3D=3D IMX8Q_HSIO_LANE0) /* i.MX8QXP */ + index =3D IMX8Q_HSIO_LANE0_PCIE_PHY; + else if (lane_mask =3D=3D IMX8Q_HSIO_LANE1) /* i.MX8QM */ + index =3D IMX8Q_HSIO_LANE1_PCIE_PHY; + else if (lane_mask =3D=3D IMX8Q_HSIO_LANE2) /* i.MX8QM */ + index =3D IMX8Q_HSIO_LANE2_PHY; + else + return -EINVAL; + } else { /* PCIEA */ + if (lane_mask =3D=3D (IMX8Q_HSIO_LANE0 | IMX8Q_HSIO_LANE1)) + index =3D IMX8Q_HSIO_LANE0_1_PCIE_PHY; + else if (lane_mask =3D=3D IMX8Q_HSIO_LANE0) + index =3D IMX8Q_HSIO_LANE0_PCIE_PHY; + else + return -EINVAL; + } + break; + case PHY_TYPE_SATA: + index =3D IMX8Q_HSIO_LANE2_PHY; + break; + default: + return -EINVAL; + } + + return index; +} + +static int imx_hsio_init(struct phy *phy) +{ + int ret, i; + struct imx_hsio_phy_mix *pmix =3D phy_get_drvdata(phy); + struct imx_hsio_priv *priv =3D pmix->priv; + struct device *dev =3D priv->dev; + + /* Assign clocks refer to different modes */ + switch (pmix->phy_type) { + case PHY_TYPE_PCIE: + if (pmix->ctrl_index =3D=3D 0) { /* PCIEA */ + pmix->pmix_mode =3D PHY_MODE_PCIE; + pmix->ctrl_off =3D 0; + pmix->phy_off =3D 0; + + for (i =3D 0; i < LANE_NUM_CLKS; i++) { + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE0_PCIE_PHY) { + pmix->lane[0].clks[i].id =3D lan0_pcie_clks[i]; + } else { /* 2 lanes are bound to PCIEA */ + pmix->lane[0].clks[i].id =3D lan0_pcie_clks[i]; + pmix->lane[1].clks[i].id =3D lan1_pciea_clks[i]; + } + } + } else { /* PCIEB */ + pmix->pmix_mode =3D PHY_MODE_PCIE; + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE0_PCIE_PHY) { + /* i.MX8QXP */ + pmix->ctrl_off =3D 0; + pmix->phy_off =3D 0; + } else { + /* + * On i.MX8QM, only second or third lane can be + * bound to PCIEB. + */ + pmix->ctrl_off =3D SZ_64K; + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE1_PCIE_PHY) + pmix->phy_off =3D 0; + else /* the third lane is bound to PCIEB */ + pmix->phy_off =3D SZ_64K; + } + + for (i =3D 0; i < LANE_NUM_CLKS; i++) { + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE1_PCIE_PHY) + pmix->lane[0].clks[i].id =3D lan1_pcieb_clks[i]; + else if (pmix->idx =3D=3D IMX8Q_HSIO_LANE2_PHY) + pmix->lane[0].clks[i].id =3D lan2_pcieb_clks[i]; + else /* i.MX8QXP only has PCIEB, idx is 0 */ + pmix->lane[0].clks[i].id =3D lan0_pcie_clks[i]; + } + } + break; + case PHY_TYPE_SATA: + /* On i.MX8QM, only the third lane can be bound to SATA */ + pmix->ctrl_off =3D SZ_128K; + pmix->pmix_mode =3D PHY_MODE_SATA; + pmix->phy_off =3D SZ_64K; + + for (i =3D 0; i < LANE_NUM_CLKS; i++) + pmix->lane[0].clks[i].id =3D lan2_sata_clks[i]; + break; + default: + return -EINVAL; + } + + /* Fetch clocks and enable them */ + ret =3D devm_clk_bulk_get(dev, LANE_NUM_CLKS, pmix->lane[0].clks); + if (ret) + return ret; + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE0_1_PCIE_PHY) { + ret =3D devm_clk_bulk_get(dev, LANE_NUM_CLKS, pmix->lane[1].clks); + if (ret) + return ret; + } + ret =3D clk_bulk_prepare_enable(LANE_NUM_CLKS, pmix->lane[0].clks); + if (ret) + return ret; + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE0_1_PCIE_PHY) { + /* Enable the second lane's clocks */ + ret =3D clk_bulk_prepare_enable(LANE_NUM_CLKS, + pmix->lane[1].clks); + if (ret) { + clk_bulk_disable_unprepare(LANE_NUM_CLKS, + pmix->lane[0].clks); + return ret; + } + } + + /* allow the clocks to stabilize */ + usleep_range(200, 500); + return 0; +} + +static int imx_hsio_exit(struct phy *phy) +{ + struct imx_hsio_phy_mix *pmix =3D phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(LANE_NUM_CLKS, pmix->lane[0].clks); + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE0_1_PCIE_PHY) + /* Disable the clocks used by sencond lane of the PHY */ + clk_bulk_disable_unprepare(LANE_NUM_CLKS, pmix->lane[1].clks); + + return 0; +} + +static void imx_hsio_pcie_phy_resets(struct phy *phy) +{ + struct imx_hsio_phy_mix *pmix =3D phy_get_drvdata(phy); + struct imx_hsio_priv *priv =3D pmix->priv; + + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2, + HSIO_BUTTON_RST_N); + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2, + HSIO_PERST_N); + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2, + HSIO_POWER_UP_RST_N); + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2, + HSIO_BUTTON_RST_N); + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2, + HSIO_PERST_N); + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2, + HSIO_POWER_UP_RST_N); + + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE0_1_PCIE_PHY) { + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_APB_RSTN_0); + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_PIPE_RSTN_0_MASK); + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_APB_RSTN_1); + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_PIPE_RSTN_1_MASK); + } else if (pmix->idx =3D=3D IMX8Q_HSIO_LANE1_PCIE_PHY) { + /* The second pmix */ + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_APB_RSTN_1); + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_PIPE_RSTN_1_MASK); + } else { + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_APB_RSTN_0); + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_PIPE_RSTN_0_MASK); + } +} + +static void imx_hsio_sata_phy_resets(struct phy *phy) +{ + struct imx_hsio_phy_mix *pmix =3D phy_get_drvdata(phy); + struct imx_hsio_priv *priv =3D pmix->priv; + + /* clear PHY RST, then set it */ + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, + HSIO_EPCS_PHYRESET_N); + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, + HSIO_EPCS_PHYRESET_N); + + /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */ + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, HSIO_RESET_N); + udelay(1); + regmap_clear_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, + HSIO_RESET_N); + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, HSIO_RESET_N); +} + +static void imx_hsio_configure_clk_pad(struct phy *phy) +{ + bool pll =3D false; + u32 pad_mode; + struct imx_hsio_phy_mix *pmix =3D phy_get_drvdata(phy); + struct imx_hsio_priv *priv =3D pmix->priv; + + pad_mode =3D priv->refclk_pad; + if (pad_mode =3D=3D IMX8_PCIE_REFCLK_PAD_OUTPUT) { + pll =3D true; + regmap_update_bits(priv->misc, HSIO_CTRL0, + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_MASK, + HSIO_IOB_A_0_TXOE | HSIO_IOB_A_0_M1M0_2); + } + + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_RXENA, + pll ? 0 : HSIO_IOB_RXENA); + regmap_update_bits(priv->misc, HSIO_CTRL0, HSIO_IOB_TXENA, + pll ? HSIO_IOB_TXENA : 0); +} + +static int imx_hsio_power_on(struct phy *phy) +{ + int ret; + u32 val, addr, cond; + struct imx_hsio_phy_mix *pmix =3D phy_get_drvdata(phy); + struct imx_hsio_priv *priv =3D pmix->priv; + + if (pmix->pmix_mode =3D=3D PHY_MODE_PCIE) + imx_hsio_pcie_phy_resets(phy); + else /* SATA */ + regmap_set_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_APB_RSTN_0); + + if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2PCIEB) + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PCIE_AB_SELECT); + if (priv->hsio_cfg & IMX8Q_HSIO_CFG_PCIEAX2SATA) + regmap_set_bits(priv->misc, HSIO_CTRL0, HSIO_PHYX1_EPCS_SEL); + + imx_hsio_configure_clk_pad(phy); + + if (pmix->pmix_mode =3D=3D PHY_MODE_SATA) { + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, + HSIO_EPCS_TXDEEMP); + regmap_set_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, + HSIO_EPCS_TXDEEMP_SEL); + + imx_hsio_sata_phy_resets(phy); + } else { + /* Toggle apb_pclk to make sure PM_REQ_CORE_RST is cleared. */ + clk_disable_unprepare(pmix->lane[0].clks[0].clk); + mdelay(1); + ret =3D clk_prepare_enable(pmix->lane[0].clks[0].clk); + if (ret) { + dev_err(priv->dev, "unable to enable phy apb_pclk\n"); + return ret; + } + + addr =3D pmix->ctrl_off + HSIO_PCIE_STS0; + cond =3D HSIO_PM_REQ_CORE_RST; + ret =3D regmap_read_poll_timeout(priv->ctrl, addr, val, + (val & cond) =3D=3D 0, + PHY_INIT_WAIT_USLEEP_MAX, + PHY_INIT_WAIT_TIMEOUT); + if (ret) { + dev_err(priv->dev, "HSIO_PM_REQ_CORE_RST is set\n"); + return ret; + } + } + + /* Polling to check the PHY is ready or not. */ + if (pmix->idx =3D=3D IMX8Q_HSIO_LANE1_PCIE_PHY) + cond =3D HSIO_LANE1_TX_PLL_LOCK; + else + cond =3D HSIO_LANE0_TX_PLL_LOCK; + + ret =3D regmap_read_poll_timeout(priv->phy, pmix->phy_off + HSIO_PHY_STS0, + val, ((val & cond) =3D=3D cond), + PHY_INIT_WAIT_USLEEP_MAX, + PHY_INIT_WAIT_TIMEOUT); + if (ret) { + dev_err(priv->dev, "IMX8Q PHY%d PLL lock timeout\n", pmix->idx); + return ret; + } + dev_info(priv->dev, "IMX8Q PHY%d PLL is locked\n", pmix->idx); + + if (pmix->pmix_mode =3D=3D PHY_MODE_SATA) { + cond =3D HSIO_REG48_PMA_RDY; + ret =3D read_poll_timeout(readb, val, ((val & cond) =3D=3D cond), + PHY_INIT_WAIT_USLEEP_MAX, + PHY_INIT_WAIT_TIMEOUT, false, + priv->base + HSIO_REG48_PMA_STATUS); + if (ret) + dev_err(priv->dev, "PHY calibration is timeout\n"); + else + dev_info(priv->dev, "PHY calibration is done\n"); + } + + return ret; +} + +static int imx_hsio_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + u32 val; + struct imx_hsio_phy_mix *pmix =3D phy_get_drvdata(phy); + struct imx_hsio_priv *priv =3D pmix->priv; + + if (pmix->pmix_mode !=3D mode) + return -EINVAL; + + val =3D (mode =3D=3D PHY_MODE_PCIE) ? HSIO_MODE_PCIE : HSIO_MODE_SATA; + val =3D FIELD_PREP(HSIO_MODE_MASK, val); + regmap_update_bits(priv->phy, pmix->phy_off + HSIO_CTRL0, + HSIO_MODE_MASK, val); + + switch (submode) { + case PHY_MODE_PCIE_RC: + val =3D FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT); + break; + case PHY_MODE_PCIE_EP: + val =3D FIELD_PREP(HSIO_DEVICE_TYPE_MASK, PCI_EXP_TYPE_ENDPOINT); + break; + default: /* Support only PCIe EP and RC now. */ + return 0; + } + if (submode) + regmap_update_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL0, + HSIO_DEVICE_TYPE_MASK, val); + + return 0; +} + +static int imx_hsio_set_speed(struct phy *phy, int speed) +{ + struct imx_hsio_phy_mix *pmix =3D phy_get_drvdata(phy); + struct imx_hsio_priv *priv =3D pmix->priv; + + regmap_update_bits(priv->ctrl, pmix->ctrl_off + HSIO_CTRL2, + HSIO_LTSSM_ENABLE, + speed ? HSIO_LTSSM_ENABLE : 0); + return 0; +} + +static const struct phy_ops imx_hsio_ops =3D { + .init =3D imx_hsio_init, + .exit =3D imx_hsio_exit, + .power_on =3D imx_hsio_power_on, + .set_mode =3D imx_hsio_set_mode, + .set_speed =3D imx_hsio_set_speed, + .owner =3D THIS_MODULE, +}; + +static const struct imx_hsio_drvdata imx8qxp_hsio_drvdata =3D { + .phy_mix_num =3D 0x1, +}; + +static const struct imx_hsio_drvdata imx_hsio_drvdata =3D { + .phy_mix_num =3D 0x4, +}; + +static const struct of_device_id imx_hsio_of_match[] =3D { + {.compatible =3D "fsl,imx8qm-hsio", .data =3D &imx_hsio_drvdata}, + {.compatible =3D "fsl,imx8qxp-hsio", .data =3D &imx8qxp_hsio_drvdata}, + { }, +}; +MODULE_DEVICE_TABLE(of, imx_hsio_of_match); + +static struct phy *imx_hsio_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct imx_hsio_priv *priv =3D dev_get_drvdata(dev); + int phy_type =3D args->args[0]; + int ctrl_index =3D args->args[1]; + int idx, lane_mask =3D args->args[2]; + + idx =3D imx_hsio_get_idx(phy_type, ctrl_index, lane_mask); + if (idx < 0 || idx >=3D priv->drvdata->phy_mix_num) + return ERR_PTR(-EINVAL); + priv->pmix[idx].phy_type =3D phy_type; + priv->pmix[idx].ctrl_index =3D ctrl_index; + priv->pmix[idx].idx =3D idx; + + return priv->pmix[idx].phy; +} + +static int imx_hsio_probe(struct platform_device *pdev) +{ + int i; + void __iomem *off; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + const struct of_device_id *of_id; + struct imx_hsio_priv *priv; + struct phy_provider *provider; + + of_id =3D of_match_device(imx_hsio_of_match, dev); + if (!of_id) + return -EINVAL; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->dev =3D &pdev->dev; + priv->drvdata =3D of_device_get_match_data(dev); + + /* Get HSIO configuration mode */ + of_property_read_u32(np, "fsl,hsio-cfg", &priv->hsio_cfg); + /* Get PHY refclk pad mode */ + if (of_property_read_u32(np, "fsl,refclk-pad-mode", &priv->refclk_pad)) + priv->refclk_pad =3D IMX8_PCIE_REFCLK_PAD_OUTPUT; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + off =3D devm_platform_ioremap_resource_byname(pdev, "phy"); + priv->phy =3D devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(priv->phy)) + return dev_err_probe(dev, PTR_ERR(priv->phy), + "unable to find phy csr registers\n"); + + off =3D devm_platform_ioremap_resource_byname(pdev, "ctrl"); + priv->ctrl =3D devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(priv->ctrl)) + return dev_err_probe(dev, PTR_ERR(priv->ctrl), + "unable to find ctrl csr registers\n"); + + off =3D devm_platform_ioremap_resource_byname(pdev, "misc"); + priv->misc =3D devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(priv->misc)) + return dev_err_probe(dev, PTR_ERR(priv->misc), + "unable to find misc csr registers\n"); + + for (i =3D 0; i < priv->drvdata->phy_mix_num; i++) { + struct imx_hsio_phy_mix *pmix =3D &priv->pmix[i]; + struct phy *phy; + + memset(pmix, 0, sizeof(*pmix)); + + phy =3D devm_phy_create(&pdev->dev, NULL, &imx_hsio_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + pmix->priv =3D priv; + pmix->phy =3D phy; + pmix->idx =3D i; + phy_set_drvdata(phy, pmix); + } + + dev_set_drvdata(dev, priv); + dev_set_drvdata(&pdev->dev, priv); + + provider =3D devm_of_phy_provider_register(&pdev->dev, imx_hsio_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static struct platform_driver imx_hsio_driver =3D { + .probe =3D imx_hsio_probe, + .driver =3D { + .name =3D "imx8qm-hsio-phy", + .of_match_table =3D imx_hsio_of_match, + } +}; +module_platform_driver(imx_hsio_driver); + +MODULE_DESCRIPTION("FSL IMX8QM HSIO SERDES PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.37.1