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Tue, 23 Apr 2024 10:33:43 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 43NAXfYD003612; Tue, 23 Apr 2024 10:33:41 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTP id 3xm6ske0ba-1; Tue, 23 Apr 2024 10:33:41 +0000 Received: from APTAIPPMTA01.qualcomm.com (APTAIPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 43NAXfth003605; Tue, 23 Apr 2024 10:33:41 GMT Received: from cbsp-sh-gv.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA01.qualcomm.com (PPS) with ESMTP id 43NAXf8t003604; Tue, 23 Apr 2024 10:33:41 +0000 Received: by cbsp-sh-gv.qualcomm.com (Postfix, from userid 4098150) id 61DC85B10; Tue, 23 Apr 2024 18:33:40 +0800 (CST) From: Qiang Yu To: mani@kernel.org, quic_jhugo@quicinc.com Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_cang@quicinc.com, quic_mrana@quicinc.com, Qiang Yu Subject: [PATCH v4 3/3] bus: mhi: host: pci_generic: Add edl callback to enter EDL Date: Tue, 23 Apr 2024 18:33:37 +0800 Message-Id: <1713868417-37856-4-git-send-email-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1713868417-37856-1-git-send-email-quic_qianyu@quicinc.com> References: <1713868417-37856-1-git-send-email-quic_qianyu@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PI4mMDUrlgJ2iEevvVBpKQW_xG_UpIwg X-Proofpoint-GUID: PI4mMDUrlgJ2iEevvVBpKQW_xG_UpIwg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_09,2024-04-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 adultscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404230028 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some of the MHI modems like SDX65 based ones are capable of entering the EDL mode as per the standard triggering mechanism defined in the MHI spec v1.2.= So let's add a common mhi_pci_generic_edl_trigger() function that triggers the= EDL mode in the device when user writes to the /sys/bus/mhi/devices/.../trigger= _edl file. Signed-off-by: Qiang Yu Reviewed-by: Jeffrey Hugo Reviewed-by: Manivannan Sadhasivam --- drivers/bus/mhi/host/pci_generic.c | 45 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 45 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_= generic.c index 51639bf..c65eaa8 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -27,12 +27,16 @@ #define PCI_VENDOR_ID_THALES 0x1269 #define PCI_VENDOR_ID_QUECTEL 0x1eac =20 +#define MHI_EDL_DB 91 +#define MHI_EDL_COOKIE 0xEDEDEDED + /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration * @name: name of the PCI module * @fw: firmware path (if any) * @edl: emergency download mode firmware path (if any) + * @edl_trigger: capable of triggering EDL mode in the device (if supporte= d) * @bar_num: PCI base address register to use for MHI MMIO register space * @dma_data_width: DMA transfer word size (32 or 64 bits) * @mru_default: default MRU size for MBIM network packets @@ -44,6 +48,7 @@ struct mhi_pci_dev_info { const char *name; const char *fw; const char *edl; + bool edl_trigger; unsigned int bar_num; unsigned int dma_data_width; unsigned int mru_default; @@ -292,6 +297,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx75_inf= o =3D { .name =3D "qcom-sdx75m", .fw =3D "qcom/sdx75m/xbl.elf", .edl =3D "qcom/sdx75m/edl.mbn", + .edl_trigger =3D true, .config =3D &modem_qcom_v2_mhiv_config, .bar_num =3D MHI_PCI_DEFAULT_BAR_NUM, .dma_data_width =3D 32, @@ -302,6 +308,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_inf= o =3D { .name =3D "qcom-sdx65m", .fw =3D "qcom/sdx65m/xbl.elf", .edl =3D "qcom/sdx65m/edl.mbn", + .edl_trigger =3D true, .config =3D &modem_qcom_v1_mhiv_config, .bar_num =3D MHI_PCI_DEFAULT_BAR_NUM, .dma_data_width =3D 32, @@ -312,6 +319,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_inf= o =3D { .name =3D "qcom-sdx55m", .fw =3D "qcom/sdx55m/sbl1.mbn", .edl =3D "qcom/sdx55m/edl.mbn", + .edl_trigger =3D true, .config =3D &modem_qcom_v1_mhiv_config, .bar_num =3D MHI_PCI_DEFAULT_BAR_NUM, .dma_data_width =3D 32, @@ -928,6 +936,40 @@ static void health_check(struct timer_list *t) mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); } =20 +static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl) +{ + void __iomem *base =3D mhi_cntrl->regs; + void __iomem *edl_db; + int ret =3D 0; + u32 val; + + ret =3D mhi_device_get_sync(mhi_cntrl->mhi_dev); + if (ret) { + dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n"); + return ret; + } + + pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); + mhi_cntrl->runtime_get(mhi_cntrl); + + ret =3D mhi_get_channel_doorbell_offset(mhi_cntrl, &val); + if (ret) + goto err_get_chdb; + + edl_db =3D base + val + (8 * MHI_EDL_DB); + + mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE)= ); + mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE)); + + mhi_soc_reset(mhi_cntrl); + +err_get_chdb: + mhi_cntrl->runtime_put(mhi_cntrl); + mhi_device_put(mhi_cntrl->mhi_dev); + + return ret; +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id = *id) { const struct mhi_pci_dev_info *info =3D (struct mhi_pci_dev_info *) id->d= river_data; @@ -962,6 +1004,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) mhi_cntrl->runtime_put =3D mhi_pci_runtime_put; mhi_cntrl->mru =3D info->mru_default; =20 + if (info->edl_trigger) + mhi_cntrl->edl_trigger =3D mhi_pci_generic_edl_trigger; + if (info->sideband_wake) { mhi_cntrl->wake_get =3D mhi_pci_wake_get_nop; mhi_cntrl->wake_put =3D mhi_pci_wake_put_nop; --=20 2.7.4