From nobody Fri Feb 13 08:19:26 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A74553365; Sun, 14 Apr 2024 20:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713126667; cv=none; b=bpvP1wwDiaGWHVkk200oRVki9/0qiCm0A/teB7BogznvqMsrBs2YuDtpO2xBXILN39XVfOzPofbsVbyDwEksjgl5oNqr/bJAU1M/LsHAnvbLaleCAWl6wi9oSrowGsuQTPRzx+MldhzYSaeF4I0fw3zCKcaO9XlZVA352xRgWJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713126667; c=relaxed/simple; bh=ZILcFQf5lWLl0n57/GyXXBnnDwkSn/HdXJkg600qHOE=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=l7Xovq9i9pDZ+AaIg5K2rlqtV/R/zlqx5BMnTg7/2QKwUtDc/HmfiesV7a24iBmFH8d8Xyyn4udehe00EaSELyCzf2LaR0325drlFl8Tkpq/KmbxOCjpAhOgDCmmgLh1iOQmWhwSMXM5J5dn/hjiaDeVlh7bkxHKbeY31doelYk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Tqa6R16a; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=TdnpdehH; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Tqa6R16a"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TdnpdehH" Date: Sun, 14 Apr 2024 20:31:01 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1713126664; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oi5htsoAUCk8AwcKz+/sQjX+L0BJg77Vt0EXo+URkEs=; b=Tqa6R16arvYOX3cNsyK+L5uGV3Qt9sfppG/F9yepkpFw9pPm2wpbkS+L/mcLUW7HlpN5aT 26M5EN3Ew34Rfg/I8deRMuFNoxpY9bDWJq+KSafkebh0vRA0gpigFN7Ax2kNP9UXkwag0/ JQI6M8Dto90DfXQ1jcWpBPh28E62JtrnNeJM52vWdnuKuA3D7DxdEli0Ghvi9VU/h9XQe8 Pz+GoPlhxpaQCnYSpugp9SyzNbUCkz0FOGyVQdmdJBjPuz8C+OuIoRklHv/ynSKdvBUDyA W6Wp7l/4pWF6iPAsbY3XJz4IbZnoLVhfAagjHDyVUZeo/T1MlQtNnz3Q169kVg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1713126664; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oi5htsoAUCk8AwcKz+/sQjX+L0BJg77Vt0EXo+URkEs=; b=TdnpdehHPzTm1DLcFPc5v9EIuB2fkNBxVQP9FpENbebT7JAZf8ALalSX31cA2dRM7nfaZi by3MSRAHe6n15EDA== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/mm] x86/pat: Introduce lookup_address_in_pgd_attr() Cc: Juergen Gross , Ingo Molnar , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20240412151258.9171-2-jgross@suse.com> References: <20240412151258.9171-2-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <171312666157.10875.6904655081631858730.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/mm branch of tip: Commit-ID: ceb647b4b529fdeca9021cd34486f5a170746bda Gitweb: https://git.kernel.org/tip/ceb647b4b529fdeca9021cd34486f5a17= 0746bda Author: Juergen Gross AuthorDate: Fri, 12 Apr 2024 17:12:55 +02:00 Committer: Ingo Molnar CommitterDate: Sun, 14 Apr 2024 22:16:26 +02:00 x86/pat: Introduce lookup_address_in_pgd_attr() Add lookup_address_in_pgd_attr() doing the same as the already existing lookup_address_in_pgd(), but returning the effective settings of the NX and RW bits of all walked page table levels, too. This will be needed in order to match hardware behavior when looking for effective access rights, especially for detecting writable code pages. In order to avoid code duplication, let lookup_address_in_pgd() call lookup_address_in_pgd_attr() with dummy parameters. Signed-off-by: Juergen Gross Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20240412151258.9171-2-jgross@suse.com --- arch/x86/include/asm/pgtable_types.h | 2 ++- arch/x86/mm/pat/set_memory.c | 33 ++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pg= table_types.h index 0b748ee..dd05cae 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -566,6 +566,8 @@ static inline void update_page_count(int level, unsigne= d long pages) { } extern pte_t *lookup_address(unsigned long address, unsigned int *level); extern pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, unsigned int *level); +pte_t *lookup_address_in_pgd_attr(pgd_t *pgd, unsigned long address, + unsigned int *level, bool *nx, bool *rw); extern pmd_t *lookup_pmd_address(unsigned long address); extern phys_addr_t slow_virt_to_phys(void *__address); extern int __init kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 80c9037..bfa0aae 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -657,20 +657,26 @@ static inline pgprot_t verify_rwx(pgprot_t old, pgpro= t_t new, unsigned long star =20 /* * Lookup the page table entry for a virtual address in a specific pgd. - * Return a pointer to the entry and the level of the mapping. + * Return a pointer to the entry, the level of the mapping, and the effect= ive + * NX and RW bits of all page table levels. */ -pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, - unsigned int *level) +pte_t *lookup_address_in_pgd_attr(pgd_t *pgd, unsigned long address, + unsigned int *level, bool *nx, bool *rw) { p4d_t *p4d; pud_t *pud; pmd_t *pmd; =20 *level =3D PG_LEVEL_NONE; + *nx =3D false; + *rw =3D true; =20 if (pgd_none(*pgd)) return NULL; =20 + *nx |=3D pgd_flags(*pgd) & _PAGE_NX; + *rw &=3D pgd_flags(*pgd) & _PAGE_RW; + p4d =3D p4d_offset(pgd, address); if (p4d_none(*p4d)) return NULL; @@ -679,6 +685,9 @@ pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long = address, if (p4d_leaf(*p4d) || !p4d_present(*p4d)) return (pte_t *)p4d; =20 + *nx |=3D p4d_flags(*p4d) & _PAGE_NX; + *rw &=3D p4d_flags(*p4d) & _PAGE_RW; + pud =3D pud_offset(p4d, address); if (pud_none(*pud)) return NULL; @@ -687,6 +696,9 @@ pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long = address, if (pud_leaf(*pud) || !pud_present(*pud)) return (pte_t *)pud; =20 + *nx |=3D pud_flags(*pud) & _PAGE_NX; + *rw &=3D pud_flags(*pud) & _PAGE_RW; + pmd =3D pmd_offset(pud, address); if (pmd_none(*pmd)) return NULL; @@ -695,12 +707,27 @@ pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned lon= g address, if (pmd_leaf(*pmd) || !pmd_present(*pmd)) return (pte_t *)pmd; =20 + *nx |=3D pmd_flags(*pmd) & _PAGE_NX; + *rw &=3D pmd_flags(*pmd) & _PAGE_RW; + *level =3D PG_LEVEL_4K; =20 return pte_offset_kernel(pmd, address); } =20 /* + * Lookup the page table entry for a virtual address in a specific pgd. + * Return a pointer to the entry and the level of the mapping. + */ +pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, + unsigned int *level) +{ + bool nx, rw; + + return lookup_address_in_pgd_attr(pgd, address, level, &nx, &rw); +} + +/* * Lookup the page table entry for a virtual address. Return a pointer * to the entry and the level of the mapping. *