From nobody Sun Feb 8 09:23:09 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DDB37F7E4; Mon, 4 Mar 2024 22:09:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709590147; cv=none; b=A8pAQHrMUnB47tHAsY10tiXVTYuXNY76GhTRNJSWf8U9INZ++SUZdwwtRxfUH/GkRFhd76HgOTGsic7qd3kukOAsKfF0bQEpd2FsKOPzpftoOYeX40Jq44qnmIDmE38VkLk4MFpDXQo5imMju6UBOaAp2SJ5/uXN4cG9uvzCRJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709590147; c=relaxed/simple; bh=dPrKFXwxB51o9rXq4LDtdhj8Oem95qzHnFQWHDYZHOs=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=Z2yR9uVC90HM0m0JnXRLQG8hEXtPyt3eNSyry21RInfMt/6Lyuovxp/NQbPJKzVAsvnRhCmOGptUNFgv0kqRl22JiRwT+Dogaw/jzjjN1+IgBEdjLv1YgvQaI1gOY2s9YqvHrGVpfgIJuWA9T0LuU3JyouNaTuoj0g9jet9BW5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2j7y+Xyz; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=J+CodwcS; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2j7y+Xyz"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="J+CodwcS" Date: Mon, 04 Mar 2024 22:09:03 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709590144; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Dv21JHmZMxNXPuOQ1baz2oN9Bt6KjTVY4KMegkisdRg=; b=2j7y+Xyz+TsvMSe2v1FAcLPnktETYo0Sg2ZsIkqEY+aaCbE5ZslBPqh1vEQgQuYePi5yqM l+IwhnxAm5MmjswQYCAPpGpZp1oMRWJHQ9BjZNmS8SXAsqyWPL6wX/sOsSvvHdDcckVH7b 7LxYPoJq69e9os807Fsgo4IlS1v9vdwYTplVxZuN/bthYDyT4FBfNSLWePiPqu1mz8I79/ PdY/caGiPeF4ruo6nsWkS97A/2G7oTM1Cp9ZiDLDL6PkC6lNkiF0LnxtWpuXLFlLd8MdMm ruv6AxqBw2YwMv0HjghKBKVIbSAT+3pQNihxbFs40vLCWx7cZwoYUwlQTD1W8g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709590144; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Dv21JHmZMxNXPuOQ1baz2oN9Bt6KjTVY4KMegkisdRg=; b=J+CodwcSPGs8qsHLi1SBQ+F/VfacF8WZm9DqKNP+839rm0lqX6gT985LqEjcc7Oy6/dtp2 ghKoNekOeK4Ta0Bw== From: "tip-bot2 for Ard Biesheuvel" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/boot] x86/startup_64: Simplify calculation of initial page table address Cc: Ard Biesheuvel , "Borislav Petkov (AMD)" , Tom Lendacky , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20240227151907.387873-14-ardb+git@google.com> References: <20240227151907.387873-14-ardb+git@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170959014335.398.4054915747896560002.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/boot branch of tip: Commit-ID: d6a41f184dcea0814260af2780e147022c11dca8 Gitweb: https://git.kernel.org/tip/d6a41f184dcea0814260af2780e147022= c11dca8 Author: Ard Biesheuvel AuthorDate: Tue, 27 Feb 2024 16:19:11 +01:00 Committer: Borislav Petkov (AMD) CommitterDate: Mon, 04 Mar 2024 18:12:16 +01:00 x86/startup_64: Simplify calculation of initial page table address Determining the address of the initial page table to program into CR3 involves: - taking the physical address - adding the SME encryption mask On the primary entry path, the code is mapped using a 1:1 virtual to physical translation, so the physical address can be taken directly using a RIP-relative LEA instruction. On the secondary entry path, the address can be obtained by taking the offset from the virtual kernel base (__START_kernel_map) and adding the physical kernel base. This is implemented in a slightly confusing way, so clean this up. Signed-off-by: Ard Biesheuvel Signed-off-by: Borislav Petkov (AMD) Tested-by: Tom Lendacky Link: https://lore.kernel.org/r/20240227151907.387873-14-ardb+git@google.com --- arch/x86/kernel/head_64.S | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 54207e7..b8b7118 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -111,13 +111,11 @@ SYM_CODE_START_NOALIGN(startup_64) call __startup_64 =20 /* Form the CR3 value being sure to include the CR3 modifier */ - addq $(early_top_pgt - __START_KERNEL_map), %rax + leaq early_top_pgt(%rip), %rcx + addq %rcx, %rax =20 #ifdef CONFIG_AMD_MEM_ENCRYPT mov %rax, %rdi - mov %rax, %r14 - - addq phys_base(%rip), %rdi =20 /* * For SEV guests: Verify that the C-bit is correct. A malicious @@ -126,12 +124,6 @@ SYM_CODE_START_NOALIGN(startup_64) * the next RET instruction. */ call sev_verify_cbit - - /* - * Restore CR3 value without the phys_base which will be added - * below, before writing %cr3. - */ - mov %r14, %rax #endif =20 jmp 1f @@ -171,18 +163,18 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L= _GLOBAL) /* Clear %R15 which holds the boot_params pointer on the boot CPU */ xorl %r15d, %r15d =20 + /* Derive the runtime physical address of init_top_pgt[] */ + movq phys_base(%rip), %rax + addq $(init_top_pgt - __START_KERNEL_map), %rax + /* * Retrieve the modifier (SME encryption mask if SME is active) to be * added to the initial pgdir entry that will be programmed into CR3. */ #ifdef CONFIG_AMD_MEM_ENCRYPT - movq sme_me_mask, %rax -#else - xorl %eax, %eax + addq sme_me_mask(%rip), %rax #endif =20 - /* Form the CR3 value being sure to include the CR3 modifier */ - addq $(init_top_pgt - __START_KERNEL_map), %rax 1: =20 /* @@ -212,9 +204,6 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_G= LOBAL) btsl $X86_CR4_PSE_BIT, %ecx movq %rcx, %cr4 =20 - /* Setup early boot stage 4-/5-level pagetables. */ - addq phys_base(%rip), %rax - /* * Switch to new page-table *