From nobody Tue Jul 14 22:13:03 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7C923D3A4; Mon, 4 Mar 2024 12:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709554512; cv=none; b=XLWa6pdahmQjZhV+yCj2xf257nvcjCs1LoLwUS9VSRXH+CDpGCU6W49JKSwZQZsx09DcSY/23FTLWhb/8WrDhSz6itB8VCsrv+aFat3A6QMvKxz6gvwDPGn5g6NQTiYQ4JbwhR/0GvoMvTmjVgL2HsdLPgRl1391Yu8z49zUTiU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709554512; c=relaxed/simple; bh=O4YPBXk06Z/LswFItKphIK70oMVrjDQkBBmiAgD6Ytg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=AcsCL4nw328GionqmVd70dlvsh3qcJQf5LP2nEHuPk4P2kI8JdXYD3rGpN30hLfNtFXkYIfjD1VcWlfN8T69eGrCmC1mjZ4hg8OVuHFxlHLRX70W7bCm0BBDVFa6Di1BehlbNwyNkBRKlIU220K0wGvDMwB7BRQSGF7fXty6yz0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oRLSZpbC; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2ppw8y05; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oRLSZpbC"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2ppw8y05" Date: Mon, 04 Mar 2024 12:15:07 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709554508; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=geDnCpFgvxB2oKuj16bvG/AKad282wxpMr9/+JHwrUs=; b=oRLSZpbCB5QNoPjWYrnk0rPtJeGnZBmnQPIlj2cN64PaNTfLcdCiGPm6H4CXH9Csrfn7yz iSj6FDWAKGQZ+yHbKlq+uenpD6ZOoVFlQKStI0a4kcywgxStbJC1/BoFcz6iXKOI64dzT4 AbuBibodT/n+tbyUnIpwmooIR+IRTQd4SOo4kgxRkA0WW4VfQ0L/XF1eRGBOnkq7/Eh2At LhceOOidUDw1jfpI1BK3SsTJPOqqELgRi5QZeeIpnSnwrjpY1Xrwo9wWMTa7MUmtuc0GCs Xhy78PHPR7G0cSE+qxAMHOAAWkEzroEUoszVG30JbIgoteCJxLXSA0qjmH6SOg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709554508; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=geDnCpFgvxB2oKuj16bvG/AKad282wxpMr9/+JHwrUs=; b=2ppw8y05MWorFOd7EMG30tXdeIfn8zEvSZnCKQlTVroWcRXLGmi/H+MfnQ+GMC8OgMcRGm iPotwwRHLnvzCYBg== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cleanups] x86/msr: Prepare for including into Cc: Thomas Gleixner , Ingo Molnar , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20240304005104.454678686@linutronix.de> References: <20240304005104.454678686@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170955450788.398.5285179242265335833.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cleanups branch of tip: Commit-ID: 154fcf3a788868cb87d8c2e50c0b5b3a2fe89853 Gitweb: https://git.kernel.org/tip/154fcf3a788868cb87d8c2e50c0b5b3a2= fe89853 Author: Thomas Gleixner AuthorDate: Mon, 04 Mar 2024 11:12:19 +01:00 Committer: Ingo Molnar CommitterDate: Mon, 04 Mar 2024 12:01:39 +01:00 x86/msr: Prepare for including into To clean up the per CPU insanity of UP which causes sparse to be rightfully unhappy and prevents the usage of the generic per CPU accessors on cpu_info it is necessary to include into . Including into is impossible because it ends up in header dependency hell. The problem is that includes . The inclusion of results in a compile fail where the compiler cannot longer handle an include in which references boot_cpu_data which is defined in . The only reason why is included in are the set/get_debugctlmsr() inlines. They are defined there because is such a nice dump ground for everything. In fact they belong obviously into . Move them to and fix up the resulting damage which is just exposing the reliance on random include chains. Signed-off-by: Thomas Gleixner Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20240304005104.454678686@linutronix.de --- arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/ds.c | 1 + arch/x86/include/asm/debugreg.h | 24 ++++++++++++++++++++++++ arch/x86/include/asm/fsgsbase.h | 2 +- arch/x86/include/asm/processor.h | 22 ---------------------- arch/x86/include/asm/special_insns.h | 4 ++-- arch/x86/kernel/cpu/intel_pconfig.c | 2 ++ arch/x86/kernel/cpu/rdrand.c | 1 + arch/x86/kernel/fpu/bugs.c | 2 ++ arch/x86/kernel/step.c | 2 ++ 10 files changed, 36 insertions(+), 25 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 3804f21..768d141 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index d49d661..2641ba6 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -5,6 +5,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugre= g.h index 0cec92c..fdbbbfe 100644 --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -5,7 +5,9 @@ #include #include #include + #include +#include =20 DECLARE_PER_CPU(unsigned long, cpu_dr7); =20 @@ -159,4 +161,26 @@ static inline unsigned long amd_get_dr_addr_mask(unsig= ned int dr) } #endif =20 +static inline unsigned long get_debugctlmsr(void) +{ + unsigned long debugctlmsr =3D 0; + +#ifndef CONFIG_X86_DEBUGCTLMSR + if (boot_cpu_data.x86 < 6) + return 0; +#endif + rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); + + return debugctlmsr; +} + +static inline void update_debugctlmsr(unsigned long debugctlmsr) +{ +#ifndef CONFIG_X86_DEBUGCTLMSR + if (boot_cpu_data.x86 < 6) + return; +#endif + wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); +} + #endif /* _ASM_X86_DEBUGREG_H */ diff --git a/arch/x86/include/asm/fsgsbase.h b/arch/x86/include/asm/fsgsbas= e.h index 35cff5f..9e7e8ca 100644 --- a/arch/x86/include/asm/fsgsbase.h +++ b/arch/x86/include/asm/fsgsbase.h @@ -6,7 +6,7 @@ =20 #ifdef CONFIG_X86_64 =20 -#include +#include =20 /* * Read/write a task's FSBASE or GSBASE. This returns the value that diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 26620d7..d2ef4f5 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -576,28 +576,6 @@ extern void cpu_init(void); extern void cpu_init_exception_handling(void); extern void cr4_init(void); =20 -static inline unsigned long get_debugctlmsr(void) -{ - unsigned long debugctlmsr =3D 0; - -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) - return 0; -#endif - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); - - return debugctlmsr; -} - -static inline void update_debugctlmsr(unsigned long debugctlmsr) -{ -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) - return; -#endif - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); -} - extern void set_task_blockstep(struct task_struct *task, bool on); =20 /* Boot loader type from the setup header: */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index 48f8dd4..f13df37 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -2,11 +2,11 @@ #ifndef _ASM_X86_SPECIAL_INSNS_H #define _ASM_X86_SPECIAL_INSNS_H =20 - #ifdef __KERNEL__ - #include #include + +#include #include #include =20 diff --git a/arch/x86/kernel/cpu/intel_pconfig.c b/arch/x86/kernel/cpu/inte= l_pconfig.c index 0771a90..5be2b17 100644 --- a/arch/x86/kernel/cpu/intel_pconfig.c +++ b/arch/x86/kernel/cpu/intel_pconfig.c @@ -7,6 +7,8 @@ * Author: * Kirill A. Shutemov */ +#include +#include =20 #include #include diff --git a/arch/x86/kernel/cpu/rdrand.c b/arch/x86/kernel/cpu/rdrand.c index 26a427f..eeac00d 100644 --- a/arch/x86/kernel/cpu/rdrand.c +++ b/arch/x86/kernel/cpu/rdrand.c @@ -6,6 +6,7 @@ * Authors: Fenghua Yu , * H. Peter Anvin */ +#include =20 #include #include diff --git a/arch/x86/kernel/fpu/bugs.c b/arch/x86/kernel/fpu/bugs.c index a06b876..edbafc5 100644 --- a/arch/x86/kernel/fpu/bugs.c +++ b/arch/x86/kernel/fpu/bugs.c @@ -2,6 +2,8 @@ /* * x86 FPU bug checks: */ +#include + #include #include =20 diff --git a/arch/x86/kernel/step.c b/arch/x86/kernel/step.c index 8e2b255..3e29526 100644 --- a/arch/x86/kernel/step.c +++ b/arch/x86/kernel/step.c @@ -6,7 +6,9 @@ #include #include #include + #include +#include #include =20 unsigned long convert_ip_to_linear(struct task_struct *child, struct pt_re= gs *regs)