From nobody Sun Feb 8 23:28:00 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28FDE1E4B9; Tue, 20 Feb 2024 01:02:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708390933; cv=none; b=OIt6zsMFx6diXcjuPeGs+wsV9bmKdmqXdudtDRZUT1poaaB8vLlDo2QOGDnfnQKUzdsp43p/uybCNEzwAJcEQze/y+OiA4muB2GyVkBqTFIMzBV4Ab3lHeOLqWQtTEwgiwQ1tIHCa1VQTtNPgwi3KZc0mo85uHqwlfXQGPZNXv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708390933; c=relaxed/simple; bh=ItdoPLpGx6piTWvrxHODqmv30kLP3Gxe0J2Nz70hda4=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=KF7YQvfoQdSq975ugxoEr7rZUGi9I97KugYuO68/3XjV1jK1qM5LyGNAaGIeNruiLfIL5lIppU1vlK/GJvbNS7cfRB7eM/PnVPEkHTV5rGdgxKWW8dMrn+HfVtFDv0EZVTGTO5quw5GNaww5aacrcNxBpKkuT+DUesk7Y5pPuDc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=4ngIHsI/; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0pQJiAja; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4ngIHsI/"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0pQJiAja" Date: Tue, 20 Feb 2024 01:02:07 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1708390928; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=5HueHOvF9wc6rlDxHIpz6MwKLt9Wh96gKmMB8KfdNr4=; b=4ngIHsI/V5+uA3+K0cMw8/knCeXjE+YlZDvJ5KjuuqBkWgEBwkxGUURmoQB7IqpD1dTi74 W/gxITVoembrV/3BANQbJ3XUBF+1pfO8z02QBVjdvlGg9wdqc2vL5CLmsc977uedxI1PkZ GbsuEZ6CxLvGr7+Wc/zQe8ZFZYgfKoCMUiY6lleMg0Ka2NX/M+zeL3Nfq204BIZDVNTrrG dvFTzbIaRfjaaQmk2Lp3YSYBstDA3UtB+Gj2LzqpLPSXK1lOOlLot1gNV1eg7axexE1xgf Gr5VJtcrb8iZj3/3UiiRxd4l6nKNFOS4YMw+CV2ot7iPSjd1JBjAlULX9e0KeA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1708390928; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=5HueHOvF9wc6rlDxHIpz6MwKLt9Wh96gKmMB8KfdNr4=; b=0pQJiAjaSWDEE7zktsf9/bMHpAiNqmm+qA8/uCIXfQ+VeKktnl71Be8Ki3IHdH7ZXQBqS3 vGozIiWoIJ7XV2Cw== From: "tip-bot2 for Pawan Gupta" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/bugs: Add asm helpers for executing VERW Cc: Alyssa Milburn , Andrew Cooper , Peter Zijlstra , Pawan Gupta , Dave Hansen , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170839092792.398.3678407222202963581.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/urgent branch of tip: Commit-ID: baf8361e54550a48a7087b603313ad013cc13386 Gitweb: https://git.kernel.org/tip/baf8361e54550a48a7087b603313ad013= cc13386 Author: Pawan Gupta AuthorDate: Tue, 13 Feb 2024 18:21:35 -08:00 Committer: Dave Hansen CommitterDate: Mon, 19 Feb 2024 16:31:33 -08:00 x86/bugs: Add asm helpers for executing VERW MDS mitigation requires clearing the CPU buffers before returning to user. This needs to be done late in the exit-to-user path. Current location of VERW leaves a possibility of kernel data ending up in CPU buffers for memory accesses done after VERW such as: 1. Kernel data accessed by an NMI between VERW and return-to-user can remain in CPU buffers since NMI returning to kernel does not execute VERW to clear CPU buffers. 2. Alyssa reported that after VERW is executed, CONFIG_GCC_PLUGIN_STACKLEAK=3Dy scrubs the stack used by a system call. Memory accesses during stack scrubbing can move kernel stack contents into CPU buffers. 3. When caller saved registers are restored after a return from function executing VERW, the kernel stack accesses can remain in CPU buffers(since they occur after VERW). To fix this VERW needs to be moved very late in exit-to-user path. In preparation for moving VERW to entry/exit asm code, create macros that can be used in asm. Also make VERW patching depend on a new feature flag X86_FEATURE_CLEAR_CPU_BUF. Reported-by: Alyssa Milburn Suggested-by: Andrew Cooper Suggested-by: Peter Zijlstra Signed-off-by: Pawan Gupta Signed-off-by: Dave Hansen Link: https://lore.kernel.org/all/20240213-delay-verw-v8-1-a6216d83edb7%40l= inux.intel.com --- arch/x86/entry/entry.S | 23 +++++++++++++++++++++++ arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/nospec-branch.h | 13 +++++++++++++ 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/x86/entry/entry.S b/arch/x86/entry/entry.S index 8c8d38f..0033790 100644 --- a/arch/x86/entry/entry.S +++ b/arch/x86/entry/entry.S @@ -6,6 +6,9 @@ #include #include #include +#include +#include +#include =20 .pushsection .noinstr.text, "ax" =20 @@ -20,3 +23,23 @@ SYM_FUNC_END(entry_ibpb) EXPORT_SYMBOL_GPL(entry_ibpb); =20 .popsection + +/* + * Define the VERW operand that is disguised as entry code so that + * it can be referenced with KPTI enabled. This ensure VERW can be + * used late in exit-to-user path after page tables are switched. + */ +.pushsection .entry.text, "ax" + +.align L1_CACHE_BYTES, 0xcc +SYM_CODE_START_NOALIGN(mds_verw_sel) + UNWIND_HINT_UNDEFINED + ANNOTATE_NOENDBR + .word __KERNEL_DS +.align L1_CACHE_BYTES, 0xcc +SYM_CODE_END(mds_verw_sel); +/* For KVM */ +EXPORT_SYMBOL_GPL(mds_verw_sel); + +.popsection + diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index fdf723b..2b62cdd 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -95,7 +95,7 @@ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspac= e */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Exten= sion Version 2 */ -/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchr= onizes RDTSC */ +#define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* "" Clear CPU buffers using= VERW */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechani= sm */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 262e655..077083e 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -315,6 +315,17 @@ #endif .endm =20 +/* + * Macro to execute VERW instruction that mitigate transient data sampling + * attacks such as MDS. On affected systems a microcode update overloaded = VERW + * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF. + * + * Note: Only the memory operand variant of VERW clears the CPU buffers. + */ +.macro CLEAR_CPU_BUFFERS + ALTERNATIVE "", __stringify(verw _ASM_RIP(mds_verw_sel)), X86_FEATURE_CLE= AR_CPU_BUF +.endm + #else /* __ASSEMBLY__ */ =20 #define ANNOTATE_RETPOLINE_SAFE \ @@ -536,6 +547,8 @@ DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); =20 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear); =20 +extern u16 mds_verw_sel; + #include =20 /**