From nobody Mon Feb 9 00:02:44 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05574153509; Fri, 16 Feb 2024 15:17:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708096661; cv=none; b=JZlyCkM+yvoYOo0p39oJ3yMPKJpkdssU3Cp9Bv1wJz4DG4hE7ADkeVAkSzv3stnUkHhU7UOCZA57snbSNNQV6E+XEXN5KNL5ckNaQwmtmtK79xkfiLMCVCnYBzCBijLSY82j5sm6UysYjqpVEa0+ARr5uGZfkZrkTOpAXL0pVnU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708096661; c=relaxed/simple; bh=I+3YM0Sc9d/6cQd7mXs7Drrg1BF4ZhRMibyaOT0SszY=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=pfoyu5VzPW0akWdTnB/Sjm3jIQyHwV9VCO8JOjL12JJdMHt5/DL7IPqa16uL53UT+ca3n1FBW70enq0t1tMXAh8aAaSFzKmPP9Ume3kbjCOoly+lWXTnLquS3Xob8H7rqh4Yvqi3qMOtN7mgYoeSYRRpulseBZa713Lth1Cri9E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=aRpEmFXp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=lMZJoCrI; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="aRpEmFXp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="lMZJoCrI" Date: Fri, 16 Feb 2024 15:17:36 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1708096657; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Sd5Rxkj6Qpeh/8fSJdNQa3DIJfRUev+zF0vQruhTEGc=; b=aRpEmFXpJsWVNq0vMKbg8vwa3NeFLDvAq97UYxhkksqOWz8T08gjtZlRYgRiJ9ni22SkFQ 5bJV0vkHkb7aM5UySfp9q+YUI1BTsZKoiKlOiedgjAdfJY8TN62yxehO5OA5QcATYbJWTu Ud13U7Waa54KRJFcwsuDTeXrCplIdI9aeCEl4+zCZSrh7EeaBagag26dBsrtgoooAHXZkG AzI8YwFkEJBmxl3DwJSWIdBFH4F5uQBr4c3+BgGQi/wjo2aJo4g1zDn/dhWcFMOBLFpouy JQRZg2f54GrP7e2JOKSH4YqZO47Bz+h/4tLFkOJ4zFCLE+2ZUHKcu61bKpcMTg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1708096657; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Sd5Rxkj6Qpeh/8fSJdNQa3DIJfRUev+zF0vQruhTEGc=; b=lMZJoCrI4Ky2dlvmX7DfyKwStfdM8uUB7DD6yJz8+A0nUeMkMKKHRBXflQMlcS1KDJj239 Im5iSWxj/E43WiBA== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/apic] x86/cpu: Provide cpuid_read() et al. Cc: Thomas Gleixner , Juergen Gross , Sohil Mehta , Michael Kelley , "Peter Zijlstra (Intel)" , Zhang Rui , Wang Wendy , K Prateek Nayak , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <878r3mg570.ffs@tglx> References: <878r3mg570.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170809665630.398.15151652103627710582.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/apic branch of tip: Commit-ID: 43d86e3cd9a77912772cf7ad37ad94211bf7351d Gitweb: https://git.kernel.org/tip/43d86e3cd9a77912772cf7ad37ad94211= bf7351d Author: Thomas Gleixner AuthorDate: Wed, 14 Feb 2024 21:29:39 +01:00 Committer: Thomas Gleixner CommitterDate: Thu, 15 Feb 2024 22:07:36 +01:00 x86/cpu: Provide cpuid_read() et al. Provide a few helper functions to read CPUID leafs or individual registers into a data structure without requiring unions. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui Tested-by: Wang Wendy Tested-by: K Prateek Nayak Acked-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/878r3mg570.ffs@tglx --- arch/x86/include/asm/cpuid.h | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+) diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h index 9bee3e7..6b122a3 100644 --- a/arch/x86/include/asm/cpuid.h +++ b/arch/x86/include/asm/cpuid.h @@ -127,6 +127,42 @@ static inline unsigned int cpuid_edx(unsigned int op) return edx; } =20 +static inline void __cpuid_read(unsigned int leaf, unsigned int subleaf, u= 32 *regs) +{ + regs[CPUID_EAX] =3D leaf; + regs[CPUID_ECX] =3D subleaf; + __cpuid(regs + CPUID_EAX, regs + CPUID_EBX, regs + CPUID_ECX, regs + CPUI= D_EDX); +} + +#define cpuid_subleaf(leaf, subleaf, regs) { \ + static_assert(sizeof(*(regs)) =3D=3D 16); \ + __cpuid_read(leaf, subleaf, (u32 *)(regs)); \ +} + +#define cpuid_leaf(leaf, regs) { \ + static_assert(sizeof(*(regs)) =3D=3D 16); \ + __cpuid_read(leaf, 0, (u32 *)(regs)); \ +} + +static inline void __cpuid_read_reg(unsigned int leaf, unsigned int sublea= f, + enum cpuid_regs_idx regidx, u32 *reg) +{ + u32 regs[4]; + + __cpuid_read(leaf, subleaf, regs); + *reg =3D regs[regidx]; +} + +#define cpuid_subleaf_reg(leaf, subleaf, regidx, reg) { \ + static_assert(sizeof(*(reg)) =3D=3D 4); \ + __cpuid_read_reg(leaf, subleaf, regidx, (u32 *)(reg)); \ +} + +#define cpuid_leaf_reg(leaf, regidx, reg) { \ + static_assert(sizeof(*(reg)) =3D=3D 4); \ + __cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg)); \ +} + static __always_inline bool cpuid_function_is_indexed(u32 function) { switch (function) {