From nobody Sun Feb 8 09:12:35 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA59B14E2F3; Fri, 16 Feb 2024 15:17:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708096652; cv=none; b=LDoo8oW3Z++A9GaSmjvbYSWAIcXM8Wc4Nd19J+iHiHnJ+fPZr5H+GQiwPHQjl1YEMdzzrlmHSkJVyyJKIBMqbNjPXdL++nekd779fhL45A8OS2sv/FlT+9vmL6LDP2oC36JFmu9iKj4E8sOQJZAfdECkUQugjnqgV/+wGBNw1Ro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708096652; c=relaxed/simple; bh=u0vfNjz6EkPGPyptEeG9+sFywPr52PwvU05H/dZjJCs=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=hvYvoPXWPRcByF53gpeRJr8j4MZlzf7XoRXK1CXF+zLtNUynmlHud7NPZ3Bafgv9Et+hYEOPXvz6qWRVdBBZIVeWaHLQaO3dSQv3bHDNetVe7lE1loIBIAYAocUlv+k1HXGKQHGVvcmMyfn1Gzyxs1y8qO1Msd+tTGSRn+kzaIE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KnUtqP/C; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=lG7xGSGd; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KnUtqP/C"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="lG7xGSGd" Date: Fri, 16 Feb 2024 15:17:28 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1708096649; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6JL3AVNxS6+XrDGfi2ULyasbPvT1ZPYAFPvp8FlG+tM=; b=KnUtqP/CdmIc9XJn58a3Cb8BzEucQONOlRQBWkEN7prQ0d2HEeatXKQ7Vi/HaV7U1dxcEr /IBj/FJT4d5GdnU69J0w+veGcdW9fKgozbqMiO2boWLBWTTHKtq/1nJ0qqzX0LrE/EwLqd OWH7Sk4ViDXUsPgRPNJ1DdBMfMV7ruI/ilWi1tjjhhlGaJdE4VS3H2M7eboOLs68VAZVMa N9re2ILADUMMOmh/P5QL+qxa+BlyKj21pSvCsimqSa9V8M7a1aYuh4LRrlO43xfcJ8LDea oJh4tcT6X9M7KwLd6Dy/HDD+KakC+6nn0smH/OJbRJxn9VhgB+2W6fyU3xrPRw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1708096649; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6JL3AVNxS6+XrDGfi2ULyasbPvT1ZPYAFPvp8FlG+tM=; b=lG7xGSGdeZijO2gGuyxD2PGbje+b45PrP4S/pMTxSqhonRQ49fXThZhDAbvXPkQTHlxoGt fVZwU2YtIukFkeDQ== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/apic] x86/mm/numa: Use core domain size on AMD Cc: Thomas Gleixner , Juergen Gross , Sohil Mehta , Michael Kelley , Zhang Rui , Wang Wendy , K Prateek Nayak , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20240212153625.270320718@linutronix.de> References: <20240212153625.270320718@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170809664856.398.10325703229977624429.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/apic branch of tip: Commit-ID: d805a6916037a716e858a0a91d844bad1ca8f48b Gitweb: https://git.kernel.org/tip/d805a6916037a716e858a0a91d844bad1= ca8f48b Author: Thomas Gleixner AuthorDate: Tue, 13 Feb 2024 22:04:17 +01:00 Committer: Thomas Gleixner CommitterDate: Thu, 15 Feb 2024 22:07:38 +01:00 x86/mm/numa: Use core domain size on AMD cpuinfo::topo::x86_coreid_bits is about to be phased out. Use the core domain size from the topology information. Add a comment why the early MPTABLE parsing is required and decrapify the loop which sets the APIC ID to node map. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Tested-by: Zhang Rui Tested-by: Wang Wendy Tested-by: K Prateek Nayak Link: https://lore.kernel.org/r/20240212153625.270320718@linutronix.de --- arch/x86/include/asm/topology.h | 5 +++++- arch/x86/mm/amdtopology.c | 35 ++++++++++++++------------------ 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index 9bca92b..be27ef7 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -121,6 +121,11 @@ struct x86_topology_system { =20 extern struct x86_topology_system x86_topo_system; =20 +static inline unsigned int topology_get_domain_size(enum x86_topology_doma= ins dom) +{ + return x86_topo_system.dom_size[dom]; +} + extern const struct cpumask *cpu_coregroup_mask(int cpu); extern const struct cpumask *cpu_clustergroup_mask(int cpu); =20 diff --git a/arch/x86/mm/amdtopology.c b/arch/x86/mm/amdtopology.c index b3ca7d2..5681b99 100644 --- a/arch/x86/mm/amdtopology.c +++ b/arch/x86/mm/amdtopology.c @@ -54,13 +54,11 @@ static __init int find_northbridge(void) =20 int __init amd_numa_init(void) { - u64 start =3D PFN_PHYS(0); + unsigned int numnodes, cores, apicid; + u64 prevbase, start =3D PFN_PHYS(0); u64 end =3D PFN_PHYS(max_pfn); - unsigned numnodes; - u64 prevbase; - int i, j, nb; u32 nodeid, reg; - unsigned int bits, cores, apicid_base; + int i, j, nb; =20 if (!early_pci_allowed()) return -EINVAL; @@ -158,26 +156,25 @@ int __init amd_numa_init(void) return -ENOENT; =20 /* - * We seem to have valid NUMA configuration. Map apicids to nodes - * using the coreid bits from early_identify_cpu. + * We seem to have valid NUMA configuration. Map apicids to nodes + * using the size of the core domain in the APIC space. */ - bits =3D boot_cpu_data.x86_coreid_bits; - cores =3D 1 << bits; - apicid_base =3D 0; + cores =3D topology_get_domain_size(TOPO_CORE_DOMAIN); =20 /* - * get boot-time SMP configuration: + * Scan MPTABLE to map the local APIC and ensure that the boot CPU + * APIC ID is valid. This is required because on pre ACPI/SRAT + * systems IO-APICs are mapped before the boot CPU. */ early_get_smp_config(); =20 - if (boot_cpu_physical_apicid > 0) { - pr_info("BSP APIC ID: %02x\n", boot_cpu_physical_apicid); - apicid_base =3D boot_cpu_physical_apicid; - } - - for_each_node_mask(i, numa_nodes_parsed) - for (j =3D apicid_base; j < cores + apicid_base; j++) - set_apicid_to_node((i << bits) + j, i); + apicid =3D boot_cpu_physical_apicid; + if (apicid > 0) + pr_info("BSP APIC ID: %02x\n", apicid); =20 + for_each_node_mask(i, numa_nodes_parsed) { + for (j =3D 0; j < cores; j++, apicid++) + set_apicid_to_node(apicid, i); + } return 0; }