From nobody Sun Feb 8 11:19:44 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D4F545013; Mon, 12 Feb 2024 18:32:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707762754; cv=none; b=aXaGwTDpMMiy4qEiAa5imytqeb54x9i78dZqMUnNfEhueG0BHr0NXW5pXVhlqJjTdMnMZ+7N5wHBN/EyR4StrXrfRrSdOmOIWjFpYw1LsW4RyQt/UDru6LcEOfiOU8e2Mldlrl/qZ5xsUhhIJcfH9ziPP4rvjDfdk4LN0EYsWSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707762754; c=relaxed/simple; bh=ylsExcpQuE4/ivXOFWqfP5IlFPEcXTzn8+XszCdmMzQ=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=q/iT6zXveigPQ9BLZwkqF7a3qWsTgqAYHL6wk2OSUy+7x1Dwbc9rxD2BuN2p/QE93fz75gDtmz8wuK2vK2yXdfBeXcn0pkvAAW1BgG4Xe07FDlf858vpUe3oy4ucndMgn6gRERSUrlCRMrnx9NsVvla6a7U9e7ppe87ankgnNGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kF+wDFrC; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IoWPcIBz; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kF+wDFrC"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IoWPcIBz" Date: Mon, 12 Feb 2024 18:32:28 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707762749; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=wKPyqhdb+dbv1CHEaBeh9D5xWHMoS/Le1h/rJ/cnqL0=; b=kF+wDFrC79UWCl262sCj2fg1669B84ZQ0jStMZhRnztkuFDR+6RhaPXIOlWz2GF/VJL60Q BXqOXXLk6SXeJzgVwKmTbazfpZKzNd698d5RqG1Aj/ETm10sLZKL5FISRCNxRj67dNbk9l IgF9HfPyZ8Q71CPiCjvaGSE9xCpiXIYCuWYj6P6bKSOFqkbX0PMQmGsAWGN54Pp51+9Q/P XGca8VI3boz1P28mEckVg9/h8IdsCNh3/AQiXnMWaYOoi2MV/AUPVuJGOG19/QgeNuuKqN 5pXBUfEtHfuZ4kNzF47b6qvZT5KuOiQop3uUvRxsA5rX6j2mcf9rdLDaLV9Cqw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707762749; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=wKPyqhdb+dbv1CHEaBeh9D5xWHMoS/Le1h/rJ/cnqL0=; b=IoWPcIBzBj9C+3xRUVDwDpUrnUwSX4ltJ7rUzR6ppPKaETnzVdfSREnR1VrP7ZI82xHJk+ gRHkvKc123+Zx6BA== From: "tip-bot2 for Pawan Gupta" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/bugs: Add asm helpers for executing VERW Cc: Alyssa Milburn , Andrew Cooper , Peter Zijlstra , Pawan Gupta , Dave Hansen , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170776274871.398.16375339033088003561.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/urgent branch of tip: Commit-ID: 15d59300ac706c5e1d95ab867ff5734ddae92c67 Gitweb: https://git.kernel.org/tip/15d59300ac706c5e1d95ab867ff5734dd= ae92c67 Author: Pawan Gupta AuthorDate: Sun, 04 Feb 2024 23:18:59 -08:00 Committer: Dave Hansen CommitterDate: Mon, 12 Feb 2024 10:25:22 -08:00 x86/bugs: Add asm helpers for executing VERW MDS mitigation requires clearing the CPU buffers before returning to user. This needs to be done late in the exit-to-user path. Current location of VERW leaves a possibility of kernel data ending up in CPU buffers for memory accesses done after VERW such as: 1. Kernel data accessed by an NMI between VERW and return-to-user can remain in CPU buffers since NMI returning to kernel does not execute VERW to clear CPU buffers. 2. Alyssa reported that after VERW is executed, CONFIG_GCC_PLUGIN_STACKLEAK=3Dy scrubs the stack used by a system call. Memory accesses during stack scrubbing can move kernel stack contents into CPU buffers. 3. When caller saved registers are restored after a return from function executing VERW, the kernel stack accesses can remain in CPU buffers(since they occur after VERW). To fix this VERW needs to be moved very late in exit-to-user path. In preparation for moving VERW to entry/exit asm code, create macros that can be used in asm. Also make VERW patching depend on a new feature flag X86_FEATURE_CLEAR_CPU_BUF. Reported-by: Alyssa Milburn Suggested-by: Andrew Cooper Suggested-by: Peter Zijlstra Signed-off-by: Pawan Gupta Signed-off-by: Dave Hansen Link: https://lore.kernel.org/all/20240204-delay-verw-v7-1-59be2d704cb2%40l= inux.intel.com --- arch/x86/entry/entry.S | 22 ++++++++++++++++++++++ arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/nospec-branch.h | 17 +++++++++++++++++ 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/x86/entry/entry.S b/arch/x86/entry/entry.S index 8c8d38f..bd8e77c 100644 --- a/arch/x86/entry/entry.S +++ b/arch/x86/entry/entry.S @@ -6,6 +6,9 @@ #include #include #include +#include +#include +#include =20 .pushsection .noinstr.text, "ax" =20 @@ -20,3 +23,22 @@ SYM_FUNC_END(entry_ibpb) EXPORT_SYMBOL_GPL(entry_ibpb); =20 .popsection + +/* + * Defines the VERW operand that is disguised as entry code so that + * it can be referenced with KPTI enabled. This ensures VERW can be + * used late in exit-to-user path after page tables are switched. + */ +.pushsection .entry.text, "ax" + +.align L1_CACHE_BYTES, 0xcc +SYM_CODE_START_NOALIGN(mds_verw_sel) + UNWIND_HINT_UNDEFINED + ANNOTATE_NOENDBR + .word __KERNEL_DS +.align L1_CACHE_BYTES, 0xcc +SYM_CODE_END(mds_verw_sel); +/* For KVM */ +EXPORT_SYMBOL_GPL(mds_verw_sel); + +.popsection diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index fdf723b..2b62cdd 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -95,7 +95,7 @@ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspac= e */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Exten= sion Version 2 */ -/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchr= onizes RDTSC */ +#define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* "" Clear CPU buffers using= VERW */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechani= sm */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 262e655..ec85dfe 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -315,6 +315,21 @@ #endif .endm =20 +/* + * Macros to execute VERW instruction that mitigate transient data sampling + * attacks such as MDS. On affected systems a microcode update overloaded = VERW + * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF. + * + * Note: Only the memory operand variant of VERW clears the CPU buffers. + */ +.macro EXEC_VERW + verw _ASM_RIP(mds_verw_sel) +.endm + +.macro CLEAR_CPU_BUFFERS + ALTERNATIVE "", __stringify(EXEC_VERW), X86_FEATURE_CLEAR_CPU_BUF +.endm + #else /* __ASSEMBLY__ */ =20 #define ANNOTATE_RETPOLINE_SAFE \ @@ -536,6 +551,8 @@ DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); =20 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear); =20 +extern u16 mds_verw_sel; + #include =20 /**