From nobody Tue Dec 23 20:06:29 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8C6E55772; Wed, 31 Jan 2024 07:21:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706685674; cv=none; b=UYVpItk2i6bgI9+xwxcaCoW8G817nxwtVJMOzTRZSNuQKXiDw1jzxOyRvwQ8gjQrvmFGwpAlkB8dbafJrN0wZQ8+AJSBj3crL9/do218UJ0VRQRUuObc0Z+28FtFne/phmoZ5Biaj0Czg6uGkPBec4/tXIh4fglhgRWPFwbOcm0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706685674; c=relaxed/simple; bh=inx/MoK+nX1XWfZsDYJQySbJPkdyyH7g5uCrznK3rHY=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=SeVJEPfAKjblDvDEv2QT+vF9sCKdmLmMWlJ4HeckyArNMhgVsG70ROL5N5BEupvY6kHdBrM68ag/qXkFBPJH5n2csxeCxPLARJw967EkUFJsnKa+5zs43y5L+TI23NRPkxVuSpwZHLkpnocnUJgS8qYyI5q4YkZchNUpH5FBeqQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KJQ4diPd; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sBUQCrXO; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KJQ4diPd"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sBUQCrXO" Date: Wed, 31 Jan 2024 07:21:10 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706685670; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RVveiR25OSyQ6043d2mbGU7kRo7eHnFy8CfWCFHNWzU=; b=KJQ4diPdrg4+jcMMDOGCy1XFIAIEf+GG3SuZYVu0KaUIKg44h8bQBuT70hpPCMKvJxGGJx KY0BFeLH++8o5+DoitJTbey3aSvVWueeMdjXEpOkMencZZZlNwTf0SqEfgoP2XOPeba0fL hIO87AqVVCzh3z1SwsY5RF2NlLeSywUrsuco24eRh6idHCKCRJVCZLndS8b/UO7dwpnNmQ 1iz5n6lgyoXQWhINH9LRlibTtS6b1Q5wB43QoNkyaFZnJuQemou27AjPNQH6oFN31ugi28 RlL4jk5qb8kPFAKwBGHFNZKJgDnXtbvoz7OoW7BfhE9Ai8GtrHCmzS3UcWqm1A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706685670; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RVveiR25OSyQ6043d2mbGU7kRo7eHnFy8CfWCFHNWzU=; b=sBUQCrXOsMt4NYlT0Csk1kG0TXFNn12d6kWf/tiC/IMaXEij6tRgXYwSxi3DpQSEhg8mIo siekqfNrLiWA4pDg== From: "tip-bot2 for Peter Zijlstra (Intel)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/fred] x86/entry/calling: Allow PUSH_AND_CLEAR_REGS being used beyond actual entry code Cc: "Peter Zijlstra (Intel)" , Xin Li , Thomas Gleixner , Shan Kang , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20231205105030.8698-31-xin3.li@intel.com> References: <20231205105030.8698-31-xin3.li@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170668567005.398.8952019391894934362.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/fred branch of tip: Commit-ID: 8c968f4df73c62be94229c7dbbb330ba9fadbd50 Gitweb: https://git.kernel.org/tip/8c968f4df73c62be94229c7dbbb330ba9= fadbd50 Author: Peter Zijlstra (Intel) AuthorDate: Tue, 05 Dec 2023 02:50:19 -08:00 Committer: Borislav Petkov (AMD) CommitterDate: Tue, 30 Jan 2024 18:20:36 +01:00 x86/entry/calling: Allow PUSH_AND_CLEAR_REGS being used beyond actual entry= code PUSH_AND_CLEAR_REGS could be used besides actual entry code; in that case %rbp shouldn't be cleared (otherwise the frame pointer is destroyed) and UNWIND_HINT shouldn't be added. Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Xin Li Signed-off-by: Thomas Gleixner Tested-by: Shan Kang Link: https://lore.kernel.org/r/20231205105030.8698-31-xin3.li@intel.com --- arch/x86/entry/calling.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h index 9f1d947..3ff925b 100644 --- a/arch/x86/entry/calling.h +++ b/arch/x86/entry/calling.h @@ -65,7 +65,7 @@ For 32-bit we have the following conventions - kernel is = built with * for assembly code: */ =20 -.macro PUSH_REGS rdx=3D%rdx rcx=3D%rcx rax=3D%rax save_ret=3D0 +.macro PUSH_REGS rdx=3D%rdx rcx=3D%rcx rax=3D%rax save_ret=3D0 unwind_hint= =3D1 .if \save_ret pushq %rsi /* pt_regs->si */ movq 8(%rsp), %rsi /* temporarily store the return address in %rsi */ @@ -87,14 +87,17 @@ For 32-bit we have the following conventions - kernel i= s built with pushq %r13 /* pt_regs->r13 */ pushq %r14 /* pt_regs->r14 */ pushq %r15 /* pt_regs->r15 */ + + .if \unwind_hint UNWIND_HINT_REGS + .endif =20 .if \save_ret pushq %rsi /* return address on top of stack */ .endif .endm =20 -.macro CLEAR_REGS +.macro CLEAR_REGS clear_bp=3D1 /* * Sanitize registers of values that a speculation attack might * otherwise want to exploit. The lower registers are likely clobbered @@ -109,7 +112,9 @@ For 32-bit we have the following conventions - kernel i= s built with xorl %r10d, %r10d /* nospec r10 */ xorl %r11d, %r11d /* nospec r11 */ xorl %ebx, %ebx /* nospec rbx */ + .if \clear_bp xorl %ebp, %ebp /* nospec rbp */ + .endif xorl %r12d, %r12d /* nospec r12 */ xorl %r13d, %r13d /* nospec r13 */ xorl %r14d, %r14d /* nospec r14 */ @@ -117,9 +122,9 @@ For 32-bit we have the following conventions - kernel i= s built with =20 .endm =20 -.macro PUSH_AND_CLEAR_REGS rdx=3D%rdx rcx=3D%rcx rax=3D%rax save_ret=3D0 - PUSH_REGS rdx=3D\rdx, rcx=3D\rcx, rax=3D\rax, save_ret=3D\save_ret - CLEAR_REGS +.macro PUSH_AND_CLEAR_REGS rdx=3D%rdx rcx=3D%rcx rax=3D%rax save_ret=3D0 c= lear_bp=3D1 unwind_hint=3D1 + PUSH_REGS rdx=3D\rdx, rcx=3D\rcx, rax=3D\rax, save_ret=3D\save_ret unwind= _hint=3D\unwind_hint + CLEAR_REGS clear_bp=3D\clear_bp .endm =20 .macro POP_REGS pop_rdi=3D1