From nobody Wed Dec 24 14:15:29 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D79FF13A242; Thu, 25 Jan 2024 18:21:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706206898; cv=none; b=DVwdvPk8e/3k5TzXDpwqxBQQDPxNavKiGIe7MFCotCPGOnhiZ8tfZxcFz+ZcURnGq/KX+ekTBohIKMlVD2k7mkaA5EXYcX6TN4xNgC3i28UqU26lENHERiI3xW6qtLmPsHa6V2ZEi0CNodxLuOrFpL/+ruZVfDDXCoFBe+JHyao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706206898; c=relaxed/simple; bh=ilBs16Zx/EspvmyGTE2gwN1gK6EvIN7UMg3cF8k+2yA=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=MGPgBDkeW1YoXGRMajtRgK7i/LmqS0+WAkmpCFR8i/TpsrjV1hQ/OkcB/2UqN4k2A3OfH2bjVpUGOYpPMu79jr+1HXnwMvbkWFrCh1WVkFU2WIszvTo8lw3e5Uuh0pIEDTvETPSxaDW6Ajb7EiUCDono5z5Y68pZtuqF/JeN6jE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=EQ22uxjt; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=H95bCOzo; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="EQ22uxjt"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="H95bCOzo" Date: Thu, 25 Jan 2024 18:21:33 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706206894; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=opfhapgWd5sBJyKyS1cpL+Owg1lDw/SwVoorEMlQR+k=; b=EQ22uxjtdoj0Me60jrBv8QTTv4+x7kPpys78BcRuGl0IoUvPge1y09aVUDjByrKUzCDod2 qeHX2XfKmlPF1zZKqvWXAFfVu+PtlvC0h8MVrrHjMVVkJaRtNpDy7wKvExLob1rBwqibbp WOqCBTgWGa7E9WWiac1GKRuELt1JHluUr6arwL6o0g3+2jn9mdxlz39IFDpJ5HQdPiVElO Dso1lGVWEQBR1fKe6icHHHcLnqz6oHO3XYGZ5VvjC7JgaN+DvjWg1IuiiLDD40UyEzhQGW knM4WixcM/cesCmXBJLfuQW11fvZ95F6JNWIdl9BKXlzA7J80+Vqd1ZfxWAaqA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706206894; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=opfhapgWd5sBJyKyS1cpL+Owg1lDw/SwVoorEMlQR+k=; b=H95bCOzoi5JrDvnTq94Bn6DHWgrJnJm2vfwg9yWAF8ARILiA8TNmTSOrF8bLwWLPWd6GMn yl+ulIRUTkt/AbCw== From: "tip-bot2 for H. Peter Anvin (Intel)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/fred] x86/cpu: Add X86_CR4_FRED macro Cc: "H. Peter Anvin (Intel)" , Xin Li , Thomas Gleixner , Shan Kang , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20231205105030.8698-12-xin3.li@intel.com> References: <20231205105030.8698-12-xin3.li@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170620689363.398.2996630752876971026.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/fred branch of tip: Commit-ID: 22a5d8d8daf22e98eb472be6c4c9f3a195ed6025 Gitweb: https://git.kernel.org/tip/22a5d8d8daf22e98eb472be6c4c9f3a19= 5ed6025 Author: H. Peter Anvin (Intel) AuthorDate: Tue, 05 Dec 2023 02:50:00 -08:00 Committer: Thomas Gleixner CommitterDate: Thu, 25 Jan 2024 19:10:30 +01:00 x86/cpu: Add X86_CR4_FRED macro Add X86_CR4_FRED macro for the FRED bit in %cr4. This bit must not be changed after initialization, so add it to the pinned CR4 bits. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li Signed-off-by: Thomas Gleixner Tested-by: Shan Kang Link: https://lore.kernel.org/r/20231205105030.8698-12-xin3.li@intel.com --- arch/x86/include/uapi/asm/processor-flags.h | 7 +++++++ arch/x86/kernel/cpu/common.c | 5 ++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include= /uapi/asm/processor-flags.h index d898432..f1a4adc 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -139,6 +139,13 @@ #define X86_CR4_LAM_SUP_BIT 28 /* LAM for supervisor pointers */ #define X86_CR4_LAM_SUP _BITUL(X86_CR4_LAM_SUP_BIT) =20 +#ifdef __x86_64__ +#define X86_CR4_FRED_BIT 32 /* enable FRED kernel entry */ +#define X86_CR4_FRED _BITUL(X86_CR4_FRED_BIT) +#else +#define X86_CR4_FRED (0) +#endif + /* * x86-64 Task Priority Register, CR8 */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2121ec6..204f4c7 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -382,9 +382,8 @@ out: } =20 /* These bits should not change their value after CPU init is finished. */ -static const unsigned long cr4_pinned_mask =3D - X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | - X86_CR4_FSGSBASE | X86_CR4_CET; +static const unsigned long cr4_pinned_mask =3D X86_CR4_SMEP | X86_CR4_SMAP= | X86_CR4_UMIP | + X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init;