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bh=xnIpWqev2LgwO8Ow1GD+t6pP0ociRd6H33tAplbXrUk=; b=v1RVh8N+ZiGCtAGsO4yxoeGJyWHEJrIywhLLcvlCxA2lOLNifcCrTdGi9nb786xgvQeR7E RDJ71FNz36JevSDJjmAh/U0oQTE1HbVwa09E3qZ3uxb37Q39v01v34gMjMYCNh1u64iSHe TIkBV4nEvCdg6QgKaOVvm9Zvg5rXjY3g2cmuQnWr265E/qhUF9A5e5YVV0fajuHhtocYvM VjyITKQ1BtN4X4Zwmxk+DpaR9qM/b5mC15fg6+4OFCygZieVWVIPfWY+fpNBKChLSeBUKu 6Y5x/YZjuDiEpIR+CIg7II2m9nKUghQYQmwqgU0O8NTLzS6Z5Fre3+4ySDP+BA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1705605839; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xnIpWqev2LgwO8Ow1GD+t6pP0ociRd6H33tAplbXrUk=; b=l5HNtTYmSueFVepDrpX9uvpC77E617HsQX/jfGvHznnv6H85SkJ/84hFAvS6UGV1Ms6GiW jHwX1+dBF7iFQ9Aw== From: "tip-bot2 for Joshua Yeong" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/core] clocksource/timer-riscv: Add riscv_clock_shutdown callback Cc: Joshua Yeong , Anup Patel , Daniel Lezcano , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20231116105312.4800-1-joshua.yeong@starfivetech.com> References: <20231116105312.4800-1-joshua.yeong@starfivetech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <170560583897.398.3924693885126380500.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the timers/core branch of tip: Commit-ID: 6a902b118e7f30dbf0e6248f7b0f97e12c0939c3 Gitweb: https://git.kernel.org/tip/6a902b118e7f30dbf0e6248f7b0f97e12= c0939c3 Author: Joshua Yeong AuthorDate: Thu, 16 Nov 2023 18:53:12 +08:00 Committer: Daniel Lezcano CommitterDate: Wed, 27 Dec 2023 15:37:11 +01:00 clocksource/timer-riscv: Add riscv_clock_shutdown callback Add clocksource detach/shutdown callback to disable RISC-V timer interrupt = when switching out riscv timer as clock source Signed-off-by: Joshua Yeong Reviewed-by: Anup Patel Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20231116105312.4800-1-joshua.yeong@starfive= tech.com --- drivers/clocksource/timer-riscv.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 57857c0..e66dcbd 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -61,12 +61,19 @@ static int riscv_clock_next_event(unsigned long delta, return 0; } =20 +static int riscv_clock_shutdown(struct clock_event_device *evt) +{ + riscv_clock_event_stop(); + return 0; +} + static unsigned int riscv_clock_event_irq; static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) =3D { .name =3D "riscv_timer_clockevent", .features =3D CLOCK_EVT_FEAT_ONESHOT, .rating =3D 100, .set_next_event =3D riscv_clock_next_event, + .set_state_shutdown =3D riscv_clock_shutdown, }; =20 /*