From nobody Sun Dec 28 04:48:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF0E3C4332F for ; Tue, 12 Dec 2023 14:44:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376943AbjLLOo3 (ORCPT ); Tue, 12 Dec 2023 09:44:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376897AbjLLOoS (ORCPT ); Tue, 12 Dec 2023 09:44:18 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E96BAA8; Tue, 12 Dec 2023 06:44:24 -0800 (PST) Date: Tue, 12 Dec 2023 14:44:22 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1702392263; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2ie1W9GDcWrrhjsxjTMzRGHh5hSWMkXx9vnEx2J0UWI=; b=UH6ZpqBooAefwAafNfYZSfaIUonubBjb00I5CUANyik50PNtijCUXomj5ZttBm4UVcCnKp 4dH2GdIp1ozev10UzphAMGLnndpuQqCDk2f35KcZhzFTf4UshwbmDOTLzTAY5EJww/V5SN ncDnncrfMii2qtGrU91p14226EwYU6vT0UYCa7hhr3Wb7mD6hpjrOeGMAc26PZNbOCxKpw 7AaPwCskz68l47Hksy3RdsQBq6POEj58oVh1sVz7miTDHO0QWexCZicIg7Bc17q/HgX0vm ci/o7Z1WQwbdhQpHkizoDwk68337t4iHRwd3555zjugaZf6Xxg45ItPlxUQAmA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1702392263; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2ie1W9GDcWrrhjsxjTMzRGHh5hSWMkXx9vnEx2J0UWI=; b=0Ij3XX2qxEzisscW3WjpY1TZS4bE9jjJbxPLkBsKXwzQPOh/la2dvqwMQ4mZqrF55KVo0v iDeY0JsR5TFJicBQ== From: "tip-bot2 for Claudiu Beznea" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Cc: Claudiu Beznea , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Message-ID: <170239226285.398.17559475715941394376.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/core branch of tip: Commit-ID: 2eca4731cc66563b3919d8753dbd74d18c39f662 Gitweb: https://git.kernel.org/tip/2eca4731cc66563b3919d8753dbd74d18= c39f662 Author: Claudiu Beznea AuthorDate: Mon, 20 Nov 2023 13:18:17 +02:00 Committer: Thomas Gleixner CommitterDate: Tue, 12 Dec 2023 15:40:41 +01:00 irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on= register's index There are 2 TITSR registers available on the IA55 interrupt controller. Add a macro that retrieves the TITSR register offset based on it's index. This macro is useful in when adding suspend/resume support so both TITSR registers can be accessed in a for loop. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20231120111820.87398-7-claudiu.beznea.uj@bp= .renesas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index d450417..34add75 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -28,8 +28,7 @@ #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 -#define TITSR0 0x24 -#define TITSR1 0x28 +#define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 #define TSSR(n) (0x30 + ((n) * 4)) @@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsi= gned int type) struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); u32 titseln =3D hwirq - IRQC_TINT_START; - u32 offset; - u8 sense; + u8 index, sense; u32 reg; =20 switch (type & IRQ_TYPE_SENSE_MASK) { @@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) return -EINVAL; } =20 - offset =3D TITSR0; + index =3D 0; if (titseln >=3D TITSR0_MAX_INT) { titseln -=3D TITSR0_MAX_INT; - offset =3D TITSR1; + index =3D 1; } =20 raw_spin_lock(&priv->lock); - reg =3D readl_relaxed(priv->base + offset); + reg =3D readl_relaxed(priv->base + TITSR(index)); reg &=3D ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |=3D sense << (titseln * TITSEL_WIDTH); - writel_relaxed(reg, priv->base + offset); + writel_relaxed(reg, priv->base + TITSR(index)); raw_spin_unlock(&priv->lock); =20 return 0;