From nobody Sun Dec 28 10:13:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F9A6C4167B for ; Fri, 8 Dec 2023 21:15:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1574818AbjLHVPW (ORCPT ); Fri, 8 Dec 2023 16:15:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1574793AbjLHVOk (ORCPT ); Fri, 8 Dec 2023 16:14:40 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4E79172B; Fri, 8 Dec 2023 13:14:46 -0800 (PST) Date: Fri, 08 Dec 2023 21:14:44 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1702070085; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YsOwKCmmfaS1GpkqP1jhK8s98foSsaDqFlYdW7HYBso=; b=Q/kaXq07bxtoYQDS1xQKc8YTD3ae26Cj59+zjiQQL+tdPhrlvjymRQ9U3pJh+UHPhJeT9P Ka1xiuv/ElAM4vKlk4lHyosAQRH1Tr3my+pQ7g+sJcaU00tAx8EcD9G86oCF/plQ0x4Wh5 W/VLQESGeqXT1iYGSdu/EYIr2I3hCJk7J/QHnQQQUlEl/7fmZdHZuqqzpXMRrSAQa0Fl12 HqLqsLU3U3QDtpiBS99jPioJOZH0J2g7Z+H6We/tHdTwze2B+J6jj2o29x41HeNKWYKB72 zN8LLm17r+Wz7LkIP4m3/w2/kA1VfyctLN+QetFZk+PyNthur6y9n2+DGGkszg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1702070085; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YsOwKCmmfaS1GpkqP1jhK8s98foSsaDqFlYdW7HYBso=; b=iE4p6c41fsqMAJHo2EhI+OQ2t2wPaDFUzmQG/gs9m7uhCGd3CzoicLvDahXCqCzm+P3hm4 zrjc2yfOJZcR1lDw== From: "tip-bot2 for Claudiu Beznea" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] clk: renesas: r9a08g045: Add IA55 pclk and its reset Cc: Claudiu Beznea , Thomas Gleixner , Geert Uytterhoeven , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Message-ID: <170207008477.398.7455050423203256596.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/core branch of tip: Commit-ID: 63385748bce1ef169438c123c7e32c021c0b9409 Gitweb: https://git.kernel.org/tip/63385748bce1ef169438c123c7e32c021= c0b9409 Author: Claudiu Beznea AuthorDate: Mon, 20 Nov 2023 13:18:12 +02:00 Committer: Thomas Gleixner CommitterDate: Fri, 08 Dec 2023 22:06:34 +01:00 clk: renesas: r9a08g045: Add IA55 pclk and its reset IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and its reset. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-2-claudiu.beznea.uj@bp= .renesas.com --- drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 4394cb2..ea3beca 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] = __initconst =3D { =20 static const struct rzg2l_mod_clk r9a08g045_mod_clks[] =3D { DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, = 0), + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), @@ -209,6 +210,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = =3D { static const struct rzg2l_reset r9a08g045_resets[] =3D { DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0), DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), @@ -220,6 +222,7 @@ static const struct rzg2l_reset r9a08g045_resets[] =3D { =20 static const unsigned int r9a08g045_crit_mod_clks[] __initconst =3D { MOD_CLK_BASE + R9A08G045_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, };