From nobody Wed Dec 17 07:26:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45E29C4167B for ; Wed, 29 Nov 2023 10:33:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232832AbjK2KdU (ORCPT ); Wed, 29 Nov 2023 05:33:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbjK2KdT (ORCPT ); Wed, 29 Nov 2023 05:33:19 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69A04D54; Wed, 29 Nov 2023 02:33:24 -0800 (PST) Date: Wed, 29 Nov 2023 10:33:20 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1701254001; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SCrcajcmWao+TZklXlucMF71m1PrDnK6AQeOVls3bYc=; b=Ea3DqpAw0QWS/QerrwDvBT8Fa0mJ3/5LPVbBc66hO7sEHw+YnDFZ+rntHv4/7fohyAGLFD 3Gf/UcPXNroNBAGCwEUrPJk44N5q17hO7VFUGZG58xm6oSzPszoDLJZR39tS8Iw2GJdgH4 blOAKbIGJLsCnNSnUKfpebIbxmqe6GsMdo8VdlLaoYt99xVCJCLgv7GNHZGQPiHmrUjP7h 0za7FFjQIPkvWQmasRyfR49u5r7acuDbXc7oLfbFrX59hZcpyW88RJCIZvGpno9dMMBrxs nTrP2lREtQQKStd9KUVgShpgy5GKPwOprUghesMtMyqVmjWhv0BWC2oRP7vSQw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1701254001; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SCrcajcmWao+TZklXlucMF71m1PrDnK6AQeOVls3bYc=; b=2G04Gbj6JHW+8G7xOd8NSAbdi4Jny0Q9Pjh5RciT5gf4zfJ80yO+3WiYXcxH431cvhdM6d kRS3dlYfioPrr3CQ== From: "tip-bot2 for Muralidhara M K" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: ras/core] x86/MCE/AMD: Add new MA_LLC, USR_DP, and USR_CP bank types Cc: Muralidhara M K , "Borislav Petkov (AMD)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20231102114225.2006878-3-muralimk@amd.com> References: <20231102114225.2006878-3-muralimk@amd.com> MIME-Version: 1.0 Message-ID: <170125400052.398.8408207092730391634.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the ras/core branch of tip: Commit-ID: 47b744ea5e3cf855087951a74ba9f89180fa1ba5 Gitweb: https://git.kernel.org/tip/47b744ea5e3cf855087951a74ba9f8918= 0fa1ba5 Author: Muralidhara M K AuthorDate: Thu, 02 Nov 2023 11:42:23=20 Committer: Borislav Petkov (AMD) CommitterDate: Tue, 28 Nov 2023 16:26:55 +01:00 x86/MCE/AMD: Add new MA_LLC, USR_DP, and USR_CP bank types Add HWID and McaType values for new SMCA bank types. Signed-off-by: Muralidhara M K Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20231102114225.2006878-3-muralimk@amd.com --- arch/x86/include/asm/mce.h | 3 +++ arch/x86/kernel/cpu/mce/amd.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 4ad49af..de31183 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -311,6 +311,7 @@ enum smca_bank_types { SMCA_PIE, /* Power, Interrupts, etc. */ SMCA_UMC, /* Unified Memory Controller */ SMCA_UMC_V2, + SMCA_MA_LLC, /* Memory Attached Last Level Cache */ SMCA_PB, /* Parameter Block */ SMCA_PSP, /* Platform Security Processor */ SMCA_PSP_V2, @@ -326,6 +327,8 @@ enum smca_bank_types { SMCA_SHUB, /* System HUB Unit */ SMCA_SATA, /* SATA Unit */ SMCA_USB, /* USB Unit */ + SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */ + SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */ SMCA_GMI_PCS, /* GMI PCS Unit */ SMCA_XGMI_PHY, /* xGMI PHY Unit */ SMCA_WAFL_PHY, /* WAFL PHY Unit */ diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index f6c6c1e..2b46eb0 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -102,6 +102,7 @@ static const char * const smca_names[] =3D { /* UMC v2 is separate because both of them can exist in a single system. = */ [SMCA_UMC] =3D "umc", [SMCA_UMC_V2] =3D "umc_v2", + [SMCA_MA_LLC] =3D "ma_llc", [SMCA_PB] =3D "param_block", [SMCA_PSP ... SMCA_PSP_V2] =3D "psp", [SMCA_SMU ... SMCA_SMU_V2] =3D "smu", @@ -114,6 +115,8 @@ static const char * const smca_names[] =3D { [SMCA_SHUB] =3D "shub", [SMCA_SATA] =3D "sata", [SMCA_USB] =3D "usb", + [SMCA_USR_DP] =3D "usr_dp", + [SMCA_USR_CP] =3D "usr_cp", [SMCA_GMI_PCS] =3D "gmi_pcs", [SMCA_XGMI_PHY] =3D "xgmi_phy", [SMCA_WAFL_PHY] =3D "wafl_phy", @@ -164,6 +167,7 @@ static const struct smca_hwid smca_hwid_mcatypes[] =3D { { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, + { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, =20 /* Unified Memory Controller MCA type */ { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, @@ -198,6 +202,8 @@ static const struct smca_hwid smca_hwid_mcatypes[] =3D { { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, + { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, + { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) }, { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) },