From nobody Wed Dec 17 13:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0872AC61DF4 for ; Sat, 25 Nov 2023 11:16:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231945AbjKYLQR (ORCPT ); Sat, 25 Nov 2023 06:16:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbjKYLQN (ORCPT ); Sat, 25 Nov 2023 06:16:13 -0500 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2042.outbound.protection.outlook.com [40.107.92.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ED7810D2; Sat, 25 Nov 2023 03:16:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lkRxRgx7Sp18etOdAin2G6RjxOcBsW4HNk7EfYT6r8eoWSfhIbqiiq+9jtDL9zqRBWxBtAOs9mFXS42lVj+iZnLd5FLxhXWJEpPrgWdUkf6vcZMcz/pfftaykyV006ZCMSfuYMNHoFuWJgvNZF2AEH8OnfEWR5hYYehMGU5FrPfaeCmBvhjY+19LobGzGX0Wmu1cnKfs1yzzHtsSreaCgpCEJs0Zr+jUJS6VQ7qH6ktfcyTgzCmAHe+gmZkKQ1zbfVtbqtPPn1aXlB/djdzuuZPZpwbVJtTIPhuMZfuW8+wLGS4KQmqfgWTYGSUjM/7tW8tN94JK1eM4DAdMkyPGIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TrY08kOXEhF9FlCGqmeYvtnTdj0NWO6fQ/OJ+Kpc90Q=; b=PgffYNenz44mpRXz3HO3CeXb7nlhKVIZC9coj4/1eHdHEClxGNjZzleU/RukWJOWkaxwtBf5dQz8EEqDAODE5BXp+WoOErWQTNwN5p8iQkbn3EmC5MiW4Xh0y380VP7iPSA0OLTbdkt0hwDL29JytCDCyPPWKwWA2vvrr9p/NgzYkHC+C2PBselhKARbZTPnh/Own6oFlRik7zh9IxZcseQVMPnir7PQ4Jk9jeJNcfzOKTpgUv6OA/bv8ieYRVbgpnAIYVraURGGLqm8YKJSJGTqusBJmVGM0mxZybteBaBqvkc/AUTwsvtRH3ODBmZwh7Qg3Z1hXn4ZJ4r6X9SWfg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=grandegger.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TrY08kOXEhF9FlCGqmeYvtnTdj0NWO6fQ/OJ+Kpc90Q=; b=dN+7ntkg7DS01jUOI8LeqHAleLd39ParsjLcJnTWZnxxU6wNTZccimR7RPuYF7jTA2zX0XxUAsZ5O0ASjv0qByBylfZE2Xx6OsMS43GkODlGhk5KVMuobB1wpz2FvSHrtlkAw1JfSgnNlAlt79fIjBVr9EL62UF5JfwEXa5L7Cc= Received: from CYZPR19CA0014.namprd19.prod.outlook.com (2603:10b6:930:8e::6) by DM4PR12MB6206.namprd12.prod.outlook.com (2603:10b6:8:a7::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.24; Sat, 25 Nov 2023 11:16:15 +0000 Received: from CY4PEPF0000FCBF.namprd03.prod.outlook.com (2603:10b6:930:8e:cafe::6) by CYZPR19CA0014.outlook.office365.com (2603:10b6:930:8e::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.25 via Frontend Transport; Sat, 25 Nov 2023 11:16:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000FCBF.mail.protection.outlook.com (10.167.242.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7046.17 via Frontend Transport; Sat, 25 Nov 2023 11:16:15 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 25 Nov 2023 05:16:14 -0600 Received: from xhdvnc205.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Sat, 25 Nov 2023 05:16:09 -0600 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v6 1/3] dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property Date: Sat, 25 Nov 2023 16:45:31 +0530 Message-ID: <1700910933-23868-2-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1700910933-23868-1-git-send-email-srinivas.goud@amd.com> References: <1700910933-23868-1-git-send-email-srinivas.goud@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCBF:EE_|DM4PR12MB6206:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ecfe9cf-7efa-4b17-483e-08dbeda7f076 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +omPfbOLwwKmVDBrOSJOmJJK1tWSHCZgUR6Ou0ZQir7YVg+XTdJZYSGA+cJxLU2EMv257Kr+saYXP7a0wImGfdZauzkWief36lu10mx3TF9/OBBatt8EEMt4A84IqEiLqsQ31ufYfAavdP9tlWkfY9eyztWILdWOSLxREqLVnB+KylyyTCsDkNWfCAwsZyXhv4EPJeqvgQrmV6gnSfKrhNALx3K22cB8fbcFJuz1vHjwdU/7KIZWDiRZlI92zGKOIHmQ25tUB58PUvZVOBwgnPzAooHMsGBBVKL5eSZ7EJyqbCgEwvAPTLPeYtZZKRmwqb13gsg3kSkuPyVcMQQJzzwd3mgA13BV7h/IAU1DeM0hVg9P2MQimNEQ5Pn1btNpHkCKDC2pRCTCYEcxEPu6AM4tfD+zjJzts1Iv9hfCWmv9JzBthMxjXJheRMBhMP+1nb8smEXBejprlE/kNbPR9eweOLji9eHu/Dg8txJnwqre0OXkIQdpxbRvHVKEk9cE6N8wlksYnUz/NhfvmL0TpQyThEtKa5IrqfiDhs/cQGl2wAhKq4+Z01Yx9pMhaYUO7rV4F7FD+cXItLB0mgYxANsv2rQocoHkfevXvgyREHvsXDLmr0z16bXxvOwJkW57//yp/+ErQWpvtqDPc4AyQiJmNGlIWVYvaiPxd10YSCF6Jk1oOsyBwxFZ65R+kJbx+sxi4SLAJ3lRXx9eRAtA19LV1mxKs4hqToRyiPYX2GlTlyw9D47YFtWWL5vv53m4po9YFhzOfkoWa99kqkFqQgZw34oFvwUa0iKBUjeAUsHP4nXefRpZmdMI3r6Euf76M2xtvSFXXpEHj5RRW+BQQg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(376002)(396003)(346002)(230922051799003)(230173577357003)(230273577357003)(64100799003)(186009)(82310400011)(451199024)(1800799012)(46966006)(36840700001)(40470700004)(316002)(110136005)(54906003)(70206006)(70586007)(478600001)(40460700003)(6666004)(7416002)(5660300002)(921008)(41300700001)(36756003)(2906002)(4326008)(8676002)(8936002)(44832011)(86362001)(426003)(336012)(82740400003)(83380400001)(356005)(2616005)(26005)(36860700001)(47076005)(81166007)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2023 11:16:15.1568 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ecfe9cf-7efa-4b17-483e-08dbeda7f076 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCBF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6206 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ECC feature added to CAN TX_OL, TX_TL and RX FIFOs of Xilinx AXI CAN Controller. ECC is an IP configuration option where counter registers are added in IP for 1bit/2bit ECC errors. 'xlnx,has-ecc' is an optional property and added to Xilinx AXI CAN Controll= er node if ECC block enabled in the HW Signed-off-by: Srinivas Goud Acked-by: Conor Dooley --- Changes in v6: Update commit description Changes in v5: Update property description Changes in v4: Fix binding check warning Update property description Changes in v3: Update commit description Changes in v2: None Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Do= cumentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..8d4e5af 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 =20 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts =3D ; tx-fifo-depth =3D <0x40>; rx-fifo-depth =3D <0x40>; + xlnx,has-ecc; }; =20 - | --=20 2.1.1 From nobody Wed Dec 17 13:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAFDCC61DF4 for ; Sat, 25 Nov 2023 11:28:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231951AbjKYL2n (ORCPT ); Sat, 25 Nov 2023 06:28:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231960AbjKYLQT (ORCPT ); Sat, 25 Nov 2023 06:16:19 -0500 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2079.outbound.protection.outlook.com [40.107.244.79]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B889110F7; Sat, 25 Nov 2023 03:16:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IbVbbt+A+owcg2M/KfVXy+wMdmueNshqyJwb0+vVEWPrbqHihKXHX359r9sUhZ//ZOIZxRtFvr66EcsS1ILYhQ0FGNNAARZg8hC9N++dVut4vgTPYGF0h4dd6cnCO0WefqyXRQus7stihY8V4o1bB/2rBw7ZUf33RcKwukdBKtzd0BNAn82n3MFsuOWes+dq+gbsTA1gms53aFUj+f2cftKPr3Sgpy11zglrfzS7UfZ4qvO0SjQzpfLGMOMq+cn5apWLOaHbb1pCbWNQDmmXHdb0gxuJg59xSKNLE9VmMIm4eyK1zYZS75UbtGYwCcmGQgHTkNxd6rmJqQIZzvU7kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=eda2GWGYXASGLx9HOCoZOyVMyvullVjxOtAoB+qYkOA=; b=UKhihd3uE+Cn4oIpfRC903lLMzoVHyiBXbnSE46HOmLCdeCRsH4fisS0NBjxoD9uevNv97JBjTZa92/G4KZ8P7KueNsZmH4ticzGK65SPAQ7cXzu4ee1mlwMFHP167mZhs+aU5IDpWRqaHK+qdPPYQcPLuPK2OcMJLvrpQaEkzVVQkaxf5GXF+gB+leqqCIvOuWxd+rUDyhka2xOekGsXDoQWROelcdWbo5TeJ6qe1cKfAIpT4g9oephEAChSWBVt7dtdSDYriUHlrynT2Jj7QBzAwzZ9nz5W5ViicHCFNRKyK8CxSsdMW/ASITyqtGXBIbxoSCGhSJpoB2ACd8k/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=grandegger.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eda2GWGYXASGLx9HOCoZOyVMyvullVjxOtAoB+qYkOA=; b=4MP6UKI+2scRaU9CIaMxGuOQjzYXOlIWxABQw2DdNxhbVCRXU4eBwD0yWBg6gKBXxl416Z/EiJUnDoy4TMVvWjOyVeAQWGVpEHw+jJy7IvyuTyNUsFm5SeA7gPtpLthfp/G5R5EZU/q9jY61nTBx/2G1eYERmtlsy+7E5ea/djU= Received: from BN1PR14CA0008.namprd14.prod.outlook.com (2603:10b6:408:e3::13) by MN2PR12MB4174.namprd12.prod.outlook.com (2603:10b6:208:15f::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.25; Sat, 25 Nov 2023 11:16:20 +0000 Received: from SN1PEPF000252A3.namprd05.prod.outlook.com (2603:10b6:408:e3:cafe::92) by BN1PR14CA0008.outlook.office365.com (2603:10b6:408:e3::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.25 via Frontend Transport; Sat, 25 Nov 2023 11:16:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF000252A3.mail.protection.outlook.com (10.167.242.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7046.17 via Frontend Transport; Sat, 25 Nov 2023 11:16:20 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 25 Nov 2023 05:16:19 -0600 Received: from xhdvnc205.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Sat, 25 Nov 2023 05:16:14 -0600 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v6 2/3] can: xilinx_can: Add ECC support Date: Sat, 25 Nov 2023 16:45:32 +0530 Message-ID: <1700910933-23868-3-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1700910933-23868-1-git-send-email-srinivas.goud@amd.com> References: <1700910933-23868-1-git-send-email-srinivas.goud@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A3:EE_|MN2PR12MB4174:EE_ X-MS-Office365-Filtering-Correlation-Id: 5486629b-99fd-4dcf-24dd-08dbeda7f35e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gbazB0ZT0RWaHXPekZxkyQV3tv/m8Vwg6NB3pvDyDlrL/UMIfWk61kdQaQ6eCP9a2gN/4BkPGS3RIFY8XtFFJbaFUzwZULD+9o+IoCFFFKi5p1GG15IKiWGc5g0d5lr1tLd3WXbYMqWfiwa56S3IS6BQUPtNPAVYZ7N+QjqloF3j+2ShzNua0m9CrwuwA6hUTZsHGOxPuegYKK7nqLasJy0ndjZWT+OhnaVnSEpZDd/kHWcHLmC2qMBjZe9FAFrWB2taNq2Lzyl8YDBJjgKmsuMpsLc+R+93PdZxerDVoH0iICbX3BIsN7Okt5A2Zbtrd+UXq2LW6kVKztvSeGaSf3Dx0SJy4w1LwXgA+tzMLGMwFZgxQOBLRnUBoqgGOE9EF2aQc+sOXxeGDIBUa3u0XZR1FKKi9cuXZC/XQEDkPSQGcXm4ioCsHo8ja5m9tbCuqZhyqDDfFnNdIPp7w8J5neuUqp8LTiXFgonzRCEZ/qXaUx9rYdwz8gKNiG5OzYaRlvN2DTIiR1fvib0M4B0FTFhHG0mUYTHjSrwHlcPc8UK3UzMNFgzJBFRqunRuAy8Uldjem2J6ChfatQIjZ409z47aHQeh1TYZT9KNFQVyDDTWpp8TOcDkT+fVv3Je9C4ak7zIRRHOFzRll32VSehCnLq2kZel2YmQcQHkpL8gPPgblrxIcnkaTdNKwZ36aopg7DmSstQNOYOYa2wqDVr9seylY2TJggmsG2/N3qw2EN1hm7iieAVmtUqTRt4D9muMsftme/+0QboxtJpLQhhk18tg06nYZpdzClkX9Nm7WUQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(136003)(39860400002)(396003)(230922051799003)(64100799003)(451199024)(82310400011)(186009)(1800799012)(40470700004)(46966006)(36840700001)(36860700001)(36756003)(921008)(82740400003)(81166007)(356005)(40460700003)(86362001)(41300700001)(316002)(54906003)(8936002)(8676002)(70206006)(70586007)(110136005)(6666004)(478600001)(4326008)(5660300002)(7416002)(2906002)(44832011)(47076005)(40480700001)(336012)(426003)(26005)(2616005)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2023 11:16:20.0786 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5486629b-99fd-4dcf-24dd-08dbeda7f35e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4174 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ECC support for Xilinx CAN Controller, so this driver reports 1bit/2bit ECC errors for FIFO's based on ECC error interrupt. ECC feature for Xilinx CAN Controller selected through 'xlnx,has-ecc' DT property Signed-off-by: Srinivas Goud --- Changes in v6: None Changes in v5: Address review comments Change the sequence of updates the stats Use u64 stats helper function Changes in v4: None Changes in v3: None Changes in v2: Address review comments drivers/net/can/xilinx_can.c | 105 +++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 101 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index abe58f1..c8691a1 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -31,6 +31,7 @@ #include #include #include +#include =20 #define DRIVER_NAME "xilinx_can" =20 @@ -58,6 +59,13 @@ enum xcan_reg { */ XCAN_F_BTR_OFFSET =3D 0x08C, /* Data Phase Bit Timing */ XCAN_TRR_OFFSET =3D 0x0090, /* TX Buffer Ready Request */ + + /* only on AXI CAN cores */ + XCAN_ECC_CFG_OFFSET =3D 0xC8, /* ECC Configuration */ + XCAN_TXTLFIFO_ECC_OFFSET =3D 0xCC, /* TXTL FIFO ECC error counter */ + XCAN_TXOLFIFO_ECC_OFFSET =3D 0xD0, /* TXOL FIFO ECC error counter */ + XCAN_RXFIFO_ECC_OFFSET =3D 0xD4, /* RX FIFO ECC error counter */ + XCAN_AFR_EXT_OFFSET =3D 0x00E0, /* Acceptance Filter */ XCAN_FSR_OFFSET =3D 0x00E8, /* RX FIFO Status */ XCAN_TXMSG_BASE_OFFSET =3D 0x0100, /* TX Message Space */ @@ -124,6 +132,18 @@ enum xcan_reg { #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ +#define XCAN_IXR_E2BERX_MASK BIT(23) /* RX FIFO two bit ECC error */ +#define XCAN_IXR_E1BERX_MASK BIT(22) /* RX FIFO one bit ECC error */ +#define XCAN_IXR_E2BETXOL_MASK BIT(21) /* TXOL FIFO two bit ECC error */ +#define XCAN_IXR_E1BETXOL_MASK BIT(20) /* TXOL FIFO One bit ECC error */ +#define XCAN_IXR_E2BETXTL_MASK BIT(19) /* TXTL FIFO Two bit ECC error */ +#define XCAN_IXR_E1BETXTL_MASK BIT(18) /* TXTL FIFO One bit ECC error */ +#define XCAN_IXR_ECC_MASK (XCAN_IXR_E2BERX_MASK | \ + XCAN_IXR_E1BERX_MASK | \ + XCAN_IXR_E2BETXOL_MASK | \ + XCAN_IXR_E1BETXOL_MASK | \ + XCAN_IXR_E2BETXTL_MASK | \ + XCAN_IXR_E1BETXTL_MASK) #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ @@ -137,6 +157,11 @@ enum xcan_reg { #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */ #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */ #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */ +#define XCAN_ECC_CFG_REECRX_MASK BIT(2) /* Reset RX FIFO ECC error counter= s */ +#define XCAN_ECC_CFG_REECTXOL_MASK BIT(1) /* Reset TXOL FIFO ECC error cou= nters */ +#define XCAN_ECC_CFG_REECTXTL_MASK BIT(0) /* Reset TXTL FIFO ECC error cou= nters */ +#define XCAN_ECC_1BIT_CNT_MASK GENMASK(15, 0) /* FIFO ECC 1bit count mask= */ +#define XCAN_ECC_2BIT_CNT_MASK GENMASK(31, 16) /* FIFO ECC 2bit count mas= k */ =20 /* CAN register bit shift - XCAN___SHIFT */ #define XCAN_BRPR_TDC_ENABLE BIT(16) /* Transmitter Delay Compensation (T= DC) Enable */ @@ -202,6 +227,13 @@ struct xcan_devtype_data { * @devtype: Device type specific constants * @transceiver: Optional pointer to associated CAN transceiver * @rstc: Pointer to reset control + * @ecc_enable: ECC enable flag + * @ecc_2bit_rxfifo_cnt: RXFIFO 2bit ECC count + * @ecc_1bit_rxfifo_cnt: RXFIFO 1bit ECC count + * @ecc_2bit_txolfifo_cnt: TXOLFIFO 2bit ECC count + * @ecc_1bit_txolfifo_cnt: TXOLFIFO 1bit ECC count + * @ecc_2bit_txtlfifo_cnt: TXTLFIFO 2bit ECC count + * @ecc_1bit_txtlfifo_cnt: TXTLFIFO 1bit ECC count */ struct xcan_priv { struct can_priv can; @@ -221,6 +253,13 @@ struct xcan_priv { struct xcan_devtype_data devtype; struct phy *transceiver; struct reset_control *rstc; + bool ecc_enable; + u64_stats_t ecc_2bit_rxfifo_cnt; + u64_stats_t ecc_1bit_rxfifo_cnt; + u64_stats_t ecc_2bit_txolfifo_cnt; + u64_stats_t ecc_1bit_txolfifo_cnt; + u64_stats_t ecc_2bit_txtlfifo_cnt; + u64_stats_t ecc_1bit_txtlfifo_cnt; }; =20 /* CAN Bittiming constants as per Xilinx CAN specs */ @@ -523,6 +562,9 @@ static int xcan_chip_start(struct net_device *ndev) XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | XCAN_IXR_ARBLST_MASK | xcan_rx_int_mask(priv); =20 + if (priv->ecc_enable) + ier |=3D XCAN_IXR_ECC_MASK; + if (priv->devtype.flags & XCAN_FLAG_RXMNF) ier |=3D XCAN_IXR_RXMNF_MASK; =20 @@ -1127,6 +1169,50 @@ static void xcan_err_interrupt(struct net_device *nd= ev, u32 isr) priv->can.can_stats.bus_error++; } =20 + if (priv->ecc_enable && isr & XCAN_IXR_ECC_MASK) { + u32 reg_rx_ecc, reg_txol_ecc, reg_txtl_ecc; + + reg_rx_ecc =3D priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); + reg_txol_ecc =3D priv->read_reg(priv, XCAN_TXOLFIFO_ECC_OFFSET); + reg_txtl_ecc =3D priv->read_reg(priv, XCAN_TXTLFIFO_ECC_OFFSET); + + /* The counter reaches its maximum at 0xffff and does not overflow. + * Accept the small race window between reading and resetting ECC counte= rs. + */ + priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | + XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + + if (isr & XCAN_IXR_E2BERX_MASK) { + u64_stats_add(&priv->ecc_2bit_rxfifo_cnt, + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_rx_ecc)); + } + + if (isr & XCAN_IXR_E1BERX_MASK) { + u64_stats_add(&priv->ecc_1bit_rxfifo_cnt, + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_rx_ecc)); + } + + if (isr & XCAN_IXR_E2BETXOL_MASK) { + u64_stats_add(&priv->ecc_2bit_txolfifo_cnt, + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_txol_ecc)); + } + + if (isr & XCAN_IXR_E1BETXOL_MASK) { + u64_stats_add(&priv->ecc_1bit_txolfifo_cnt, + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_txol_ecc)); + } + + if (isr & XCAN_IXR_E2BETXTL_MASK) { + u64_stats_add(&priv->ecc_2bit_txtlfifo_cnt, + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_txtl_ecc)); + } + + if (isr & XCAN_IXR_E1BETXTL_MASK) { + u64_stats_add(&priv->ecc_1bit_txtlfifo_cnt, + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_txtl_ecc)); + } + } + if (cf.can_id) { struct can_frame *skb_cf; struct sk_buff *skb =3D alloc_can_err_skb(ndev, &skb_cf); @@ -1355,7 +1441,7 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_= id) struct net_device *ndev =3D (struct net_device *)dev_id; struct xcan_priv *priv =3D netdev_priv(ndev); u32 isr, ier; - u32 isr_errors; + u32 isr_errors, mask; u32 rx_int_mask =3D xcan_rx_int_mask(priv); =20 /* Get the interrupt status from Xilinx CAN */ @@ -1374,10 +1460,15 @@ static irqreturn_t xcan_interrupt(int irq, void *de= v_id) if (isr & XCAN_IXR_TXOK_MASK) xcan_tx_interrupt(ndev, isr); =20 + mask =3D XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | + XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | + XCAN_IXR_RXMNF_MASK; + + if (priv->ecc_enable) + mask |=3D XCAN_IXR_ECC_MASK; + /* Check for the type of error interrupt and Processing it */ - isr_errors =3D isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | - XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | - XCAN_IXR_RXMNF_MASK); + isr_errors =3D isr & mask; if (isr_errors) { priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); xcan_err_interrupt(ndev, isr); @@ -1796,6 +1887,7 @@ static int xcan_probe(struct platform_device *pdev) return -ENOMEM; =20 priv =3D netdev_priv(ndev); + priv->ecc_enable =3D of_property_read_bool(pdev->dev.of_node, "xlnx,has-e= cc"); priv->dev =3D &pdev->dev; priv->can.bittiming_const =3D devtype->bittiming_const; priv->can.do_set_mode =3D xcan_do_set_mode; @@ -1912,6 +2004,11 @@ static int xcan_probe(struct platform_device *pdev) priv->reg_base, ndev->irq, priv->can.clock.freq, hw_tx_max, priv->tx_max); =20 + if (priv->ecc_enable) { + /* Reset FIFO ECC counters */ + priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | + XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + } return 0; =20 err_disableclks: --=20 2.1.1 From nobody Wed Dec 17 13:52:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05795C61D9D for ; Sat, 25 Nov 2023 11:19:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231949AbjKYLQ0 (ORCPT ); Sat, 25 Nov 2023 06:16:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbjKYLQZ (ORCPT ); Sat, 25 Nov 2023 06:16:25 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2068.outbound.protection.outlook.com [40.107.220.68]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CE3B127; Sat, 25 Nov 2023 03:16:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JBO8pyYoRyP0+ZxJgUwpzZsRFjWfRz5QnOEBt5BauxEmiSX1rcZxcXOXzWiKZcFzisJNp2HjLRC/SJIVNcZ1dbs0zrZBOysat+eWipOf2dRDCG9IH2mkvfkvqGazqZVcleKXnZNW/UDfTb/x3OfFBvIOVsq9y13qCcmfMU8uSYbwbjCw4mSVFkK8MzLITJ2kg6SoqJguoJ/20HRULCpodwuWg/BJYWr5kPvPAKDg6B/OoborxLMg85igJdI83z2m76gy0QiS9w9tYe44UUG0xgV4sxTFX/Imv0O19nLC6Q/nWL60ksrOn2Imf4e7mgFHNFXtt89/JEq5fYBfj9jabQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7pbT4ZOgsylpjPkTEAy/cWXXxCkJ1vfTTpeh4wDaPSM=; b=d2aLs2NBZbB/9e5dAcOkbq7O1Tp+DEVNsLb/IVg7QEe+FD3uoroeOtgi5Giyeaph2eqs4Jf/LKey9qHByHROf2uZbFMOEBlbMbX8fgoPbNfU4w7GxUoNeA/oHQbYzMU/SG3lwcxLIhMpRAJoLVADLCxAvEB+Fvx4Xs4+IJR83npnT/yQdyW4LVX1nzb7Z36vScTWZsN/0idam+xUZkD6PWkAX5WdlEuTeXt1Yy84R6xaj9wBTKRaYREvIXy3B0Gv3YVVG8ettyqJCRFqW/Wbs+M3TRuzND8Cyp1oVoqWJjiWwMDw8z/X6PxxC0t0ADwu7hVPtHwyBWkpE3GedCUZwQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=grandegger.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7pbT4ZOgsylpjPkTEAy/cWXXxCkJ1vfTTpeh4wDaPSM=; b=4q0byuN28XqT3yBB3FDDfAjTLjuzufci7vxSxgucM6xRPMu8Kc3Sl66yYB2DGJO/r17qJAky881UhiER0eWAn5Bto8AgmgNUPDU5s7f2mFqaYc+ULtDJyo6PavJ8Zo5irhc0KuK/l6lWQbq2VO4H0qDpxWejnsQwdaeilv5ieY4= Received: from SA0PR11CA0036.namprd11.prod.outlook.com (2603:10b6:806:d0::11) by PH7PR12MB5805.namprd12.prod.outlook.com (2603:10b6:510:1d1::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.25; Sat, 25 Nov 2023 11:16:25 +0000 Received: from SN1PEPF000252A2.namprd05.prod.outlook.com (2603:10b6:806:d0:cafe::4b) by SA0PR11CA0036.outlook.office365.com (2603:10b6:806:d0::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.21 via Frontend Transport; Sat, 25 Nov 2023 11:16:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF000252A2.mail.protection.outlook.com (10.167.242.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7046.17 via Frontend Transport; Sat, 25 Nov 2023 11:16:25 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 25 Nov 2023 05:16:24 -0600 Received: from xhdvnc205.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Sat, 25 Nov 2023 05:16:19 -0600 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v6 3/3] can: xilinx_can: Add ethtool stats interface for ECC errors Date: Sat, 25 Nov 2023 16:45:33 +0530 Message-ID: <1700910933-23868-4-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1700910933-23868-1-git-send-email-srinivas.goud@amd.com> References: <1700910933-23868-1-git-send-email-srinivas.goud@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|PH7PR12MB5805:EE_ X-MS-Office365-Filtering-Correlation-Id: 359d020a-e318-4d90-8e63-08dbeda7f658 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: I65ladfwgAjGwNvmk7YrNpwF+TulsAi5A9xlu94sLkByKjezbcmch0qI+4bDE+DhTzb9fKwxXKkbwmtXGKX108TshsPEjoAdW1EPQIyImVifzUI8nEny5EcMl3jrueAKneZzOaT2/OfRf1BoD9P8LoDWPXWGzjsNc8xjZkPin0j70aV0NVtxwjLIdMh4dFQ2ZctmipSbXof38q82EFns0ctFvzxgvA6tMVyt9YWdQWKwmfEXxg6TpO50EoKBmxSEQtxCYrQNGs+xnyiCen318Pdwj2lZ5AtvnMVGJ8TsX/43yHXlWYcQiVUkRX0SOQVFELMkyTdiLCt+O8RtZqpuHaQ9nmgEyAkllfpvOkXNyDDQ4+ZJ9GY3Cxb098RTs3Gqpk6cMf3BL+zsjEKhAEuPQz0Fq9xPj12KOweeR6eK5NXo6JvU3sT2swMcO6BM9i7nwM5BaIXH2pd7fwB+g2O5b42Od6O5nZyF1NsN0kLmFLZrpO5yeriFtVnz0Pje8SnwefMIvsGDPpxdagdAAyC/bd4Ye9tc39jeDjpZE+Vf3x2jZHfaJl9C6Ua6YcWJi2hYsbgL0hd+UqKyP1Q7FzZY1rVNnGhVRLzmSA5HEHFv0AKOk/ZOYDmosccu+4QM9hmT9YJIbf4kabhr8D5V1dGwDtk4QAsZDbQk/G65eHKC8TVMPdzpAuocRhhMRu5AMObeRHa57kvSH+FmL1gX6L+Md6UQ/6Mzs5yaLGvlj826ymv3aKbkn5vDNYHVixsACGOsUzoOby8ktQdzagFuwYf8Gt//nOR4PTRL7p+Qjir8p2A= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(136003)(376002)(39860400002)(230922051799003)(451199024)(64100799003)(186009)(1800799012)(82310400011)(46966006)(40470700004)(36840700001)(40480700001)(36860700001)(81166007)(83380400001)(2616005)(47076005)(356005)(4326008)(8936002)(8676002)(86362001)(44832011)(426003)(336012)(26005)(82740400003)(40460700003)(478600001)(6666004)(110136005)(70206006)(70586007)(54906003)(316002)(2906002)(921008)(41300700001)(36756003)(7416002)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2023 11:16:25.0752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 359d020a-e318-4d90-8e63-08dbeda7f658 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5805 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ethtool stats interface for reading FIFO 1bit/2bit ECC errors informati= on. Signed-off-by: Srinivas Goud --- Changes in v6: None Changes in v5: Address review comments Add get_strings and get_sset_count stats interface Use u64 stats helper function Changes in v4: None Changes in v3: None Changes in v2: Add ethtool stats interface drivers/net/can/xilinx_can.c | 54 ++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 54 insertions(+) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index c8691a1..40c912b 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -228,6 +228,7 @@ struct xcan_devtype_data { * @transceiver: Optional pointer to associated CAN transceiver * @rstc: Pointer to reset control * @ecc_enable: ECC enable flag + * @stats_lock: Lock for synchronizing ECC errors stats * @ecc_2bit_rxfifo_cnt: RXFIFO 2bit ECC count * @ecc_1bit_rxfifo_cnt: RXFIFO 1bit ECC count * @ecc_2bit_txolfifo_cnt: TXOLFIFO 2bit ECC count @@ -254,6 +255,7 @@ struct xcan_priv { struct phy *transceiver; struct reset_control *rstc; bool ecc_enable; + spinlock_t stats_lock; /* Lock for synchronizing ECC errors stats */ u64_stats_t ecc_2bit_rxfifo_cnt; u64_stats_t ecc_1bit_rxfifo_cnt; u64_stats_t ecc_2bit_txolfifo_cnt; @@ -347,6 +349,12 @@ static const struct can_tdc_const xcan_tdc_const_canfd= 2 =3D { .tdcf_max =3D 0, }; =20 +static const char xcan_priv_flags_strings[][ETH_GSTRING_LEN] =3D { + "err-ecc-rx-2-bit", "err-ecc-rx-1-bit", + "err-ecc-txol-2-bit", "err-ecc-txol-1-bit", + "err-ecc-txtl-2-bit", "err-ecc-txtl-1-bit", +}; + /** * xcan_write_reg_le - Write a value to the device register little endian * @priv: Driver private data structure @@ -1171,6 +1179,9 @@ static void xcan_err_interrupt(struct net_device *nde= v, u32 isr) =20 if (priv->ecc_enable && isr & XCAN_IXR_ECC_MASK) { u32 reg_rx_ecc, reg_txol_ecc, reg_txtl_ecc; + unsigned long flags; + + spin_lock_irqsave(&priv->stats_lock, flags); =20 reg_rx_ecc =3D priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); reg_txol_ecc =3D priv->read_reg(priv, XCAN_TXOLFIFO_ECC_OFFSET); @@ -1182,6 +1193,8 @@ static void xcan_err_interrupt(struct net_device *nde= v, u32 isr) priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); =20 + spin_unlock_irqrestore(&priv->stats_lock, flags); + if (isr & XCAN_IXR_E2BERX_MASK) { u64_stats_add(&priv->ecc_2bit_rxfifo_cnt, FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_rx_ecc)); @@ -1637,6 +1650,44 @@ static int xcan_get_auto_tdcv(const struct net_devic= e *ndev, u32 *tdcv) return 0; } =20 +static void xcan_get_strings(struct net_device *ndev, u32 stringset, u8 *b= uf) +{ + switch (stringset) { + case ETH_SS_STATS: + memcpy(buf, &xcan_priv_flags_strings, + sizeof(xcan_priv_flags_strings)); + } +} + +static int xcan_get_sset_count(struct net_device *netdev, int sset) +{ + switch (sset) { + case ETH_SS_STATS: + return ARRAY_SIZE(xcan_priv_flags_strings); + default: + return -EOPNOTSUPP; + } +} + +static void xcan_get_ethtool_stats(struct net_device *ndev, + struct ethtool_stats *stats, u64 *data) +{ + struct xcan_priv *priv =3D netdev_priv(ndev); + unsigned long flags; + int i =3D 0; + + spin_lock_irqsave(&priv->stats_lock, flags); + + data[i++] =3D u64_stats_read(&priv->ecc_2bit_rxfifo_cnt); + data[i++] =3D u64_stats_read(&priv->ecc_1bit_rxfifo_cnt); + data[i++] =3D u64_stats_read(&priv->ecc_2bit_txolfifo_cnt); + data[i++] =3D u64_stats_read(&priv->ecc_1bit_txolfifo_cnt); + data[i++] =3D u64_stats_read(&priv->ecc_2bit_txtlfifo_cnt); + data[i++] =3D u64_stats_read(&priv->ecc_1bit_txtlfifo_cnt); + + spin_unlock_irqrestore(&priv->stats_lock, flags); +} + static const struct net_device_ops xcan_netdev_ops =3D { .ndo_open =3D xcan_open, .ndo_stop =3D xcan_close, @@ -1646,6 +1697,9 @@ static const struct net_device_ops xcan_netdev_ops = =3D { =20 static const struct ethtool_ops xcan_ethtool_ops =3D { .get_ts_info =3D ethtool_op_get_ts_info, + .get_strings =3D xcan_get_strings, + .get_sset_count =3D xcan_get_sset_count, + .get_ethtool_stats =3D xcan_get_ethtool_stats, }; =20 /** --=20 2.1.1