From nobody Thu Dec 18 22:23:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FB6FC61D85 for ; Tue, 21 Nov 2023 14:38:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234534AbjKUOig (ORCPT ); Tue, 21 Nov 2023 09:38:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234105AbjKUOib (ORCPT ); Tue, 21 Nov 2023 09:38:31 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C521113; Tue, 21 Nov 2023 06:38:27 -0800 (PST) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ALE1sCf011131; Tue, 21 Nov 2023 14:38:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=FqK8FStuSlvhx/YFe4T8dZetm2QKHmUdcZdxb0W+pHw=; b=aYP98fHcnlVkDrtZem21SQ8bg5iFbOz5t2O9NmM7BnDi3EI6WJN7RgvSWQ1S+BrmMddo ME43TmmgcXTulEt33jUtmcsFqY2UT2mddEdLtaqNbsBG7fSNezFPx2Xyml/lDjbwzJ0J 2fMmJMGahcelTTzTAEkGW2AmTV2HSToHb0P442T9BtD6bjMOpvgHxy6P0Yu2bl5UtAi2 gtvLEwBhpww2c5yWgGggIqF8XwBroaWOljo+YEQbM5kz4aKWZgNQ3b0hQi1fg+r7yeZ3 X1ACqU+QXte5s2PDhxstnABEZXUbKHuVLKMt2SUupnvwADXEPmYqfyLkZ889CnTDKF+g Tg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uguwxrp5y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Nov 2023 14:38:20 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3ALEaZ9f004089; Tue, 21 Nov 2023 14:38:17 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3uepbke7pv-1; Tue, 21 Nov 2023 14:38:17 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3ALEcGbM006075; Tue, 21 Nov 2023 14:38:16 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3ALEcGne006071; Tue, 21 Nov 2023 14:38:16 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 9DC694C8E; Tue, 21 Nov 2023 20:08:15 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 1/3] PCI: qcom: Enable cache coherency for SA8775P RC Date: Tue, 21 Nov 2023 20:08:11 +0530 Message-Id: <1700577493-18538-2-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700577493-18538-1-git-send-email-quic_msarkar@quicinc.com> References: <1700577493-18538-1-git-send-email-quic_msarkar@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oZVcOPCB51X3X3yI8grG0j88gVIF6VOL X-Proofpoint-ORIG-GUID: oZVcOPCB51X3X3yI8grG0j88gVIF6VOL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-21_08,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 mlxlogscore=782 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311210114 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In a multiprocessor system cache snooping maintains the consistency of caches. Snooping logic is disabled from HW on this platform. Cache coherency doesn=E2=80=99t work without enabling this logic. 8775 has IP version 1.34.0 so intruduce a new cfg(cfg_1_34_0) for this platform. Assign no_snoop_override flag into struct qcom_pcie_cfg and set it true in cfg_1_34_0 and enable cache snooping if this particular flag is true. Signed-off-by: Mrinmay Sarkar Reviewed-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 6902e97..76f03fc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -51,6 +51,7 @@ #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 +#define PCIE_PARF_NO_SNOOP_OVERIDE 0x3d4 #define PARF_DEVICE_TYPE 0x1000 #define PARF_BDF_TO_SID_TABLE_N 0x2000 =20 @@ -117,6 +118,10 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) =20 +/* PARF_NO_SNOOP_OVERIDE register fields */ +#define WR_NO_SNOOP_OVERIDE_EN BIT(1) +#define RD_NO_SNOOP_OVERIDE_EN BIT(3) + /* PARF_DEVICE_TYPE register fields */ #define DEVICE_TYPE_RC 0x4 =20 @@ -229,6 +234,7 @@ struct qcom_pcie_ops { =20 struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; + bool no_snoop_overide; }; =20 struct qcom_pcie { @@ -961,6 +967,13 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) =20 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) { + const struct qcom_pcie_cfg *pcie_cfg =3D pcie->cfg; + + /* Enable cache snooping for SA8775P */ + if (pcie_cfg->no_snoop_overide) + writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN, + pcie->parf + PCIE_PARF_NO_SNOOP_OVERIDE); + qcom_pcie_clear_hpc(pcie->pci); =20 return 0; @@ -1331,6 +1344,11 @@ static const struct qcom_pcie_cfg cfg_1_9_0 =3D { .ops =3D &ops_1_9_0, }; =20 +static const struct qcom_pcie_cfg cfg_1_34_0 =3D { + .ops =3D &ops_1_9_0, + .no_snoop_overide =3D true, +}; + static const struct qcom_pcie_cfg cfg_2_1_0 =3D { .ops =3D &ops_2_1_0, }; @@ -1627,7 +1645,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-msm8996", .data =3D &cfg_2_3_2 }, { .compatible =3D "qcom,pcie-qcs404", .data =3D &cfg_2_4_0 }, { .compatible =3D "qcom,pcie-sa8540p", .data =3D &cfg_1_9_0 }, - { .compatible =3D "qcom,pcie-sa8775p", .data =3D &cfg_1_9_0}, + { .compatible =3D "qcom,pcie-sa8775p", .data =3D &cfg_1_34_0}, { .compatible =3D "qcom,pcie-sc7280", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sc8180x", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sc8280xp", .data =3D &cfg_1_9_0 }, --=20 2.7.4