From nobody Tue Dec 16 19:57:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86184C00A8F for ; Tue, 24 Oct 2023 13:23:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234775AbjJXNXW (ORCPT ); Tue, 24 Oct 2023 09:23:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234499AbjJXNWF (ORCPT ); Tue, 24 Oct 2023 09:22:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4869E19BA; Tue, 24 Oct 2023 06:21:09 -0700 (PDT) Date: Tue, 24 Oct 2023 13:21:06 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1698153667; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eAfglIub128mLp7oMzUJvwkeOxDDlZuFkvy3GFnpIqc=; b=gQkrHiAkdevmSs/gm1UbOUzVgwSoZ81PmrpQHM00/u2AFHtZTAsDZvV8JF8D6j1kPViWGw d5D8HfgUDNLM3axsfL5tAXOvdR8swNgDEpM/hOLX729KSZw8gdAHiYYCspsDbv1GL6bvM7 uws6gxMpl8mVcsBcM5whxgVJG7CDiIKIRZeJQ6mhPpSX6xoPd3WgCJuS/qzJHUezhly9WW VjdJ6FBBIEACyi6EA9YERWO2nY3V+FVIz/nNGEaTb2QPEUdcym3OBICXt4a7PMioKp4HOq ZvaG1n0jflDbmiPQBo4yYYtkYwfJz3rgP4sYR00GQ3E4lGbvLqyYCTGK/167WQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1698153667; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eAfglIub128mLp7oMzUJvwkeOxDDlZuFkvy3GFnpIqc=; b=Kr6LHjGUlON6R5u2LcUL31I6UVJ+ofoOLMR4+690o8a2XQDA1umPjvHIyFCOHzI5+rmztZ amPh5EC2b0/OSuAw== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/microcode] x86/microcode/intel: Unify microcode apply() functions Cc: "Borislav Petkov (AMD)" , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20231017211722.795508212@linutronix.de> References: <20231017211722.795508212@linutronix.de> MIME-Version: 1.0 Message-ID: <169815366647.3135.18207707179078294492.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/microcode branch of tip: Commit-ID: 3973718cff1e3a5d88ea78ec28ecca2afa60b30b Gitweb: https://git.kernel.org/tip/3973718cff1e3a5d88ea78ec28ecca2af= a60b30b Author: Thomas Gleixner AuthorDate: Tue, 17 Oct 2023 23:23:44 +02:00 Committer: Borislav Petkov (AMD) CommitterDate: Tue, 24 Oct 2023 15:05:53 +02:00 x86/microcode/intel: Unify microcode apply() functions Deduplicate the early and late apply() functions. [ bp: Rename the function which does the actual application to __apply_microcode() to differentiate it from microcode_ops.apply_microcode(). ] Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20231017211722.795508212@linutronix.de --- arch/x86/kernel/cpu/microcode/intel.c | 104 ++++++++----------------- 1 file changed, 36 insertions(+), 68 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index dd2d3fd..4235c95 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -307,12 +307,12 @@ static __init struct microcode_intel *scan_microcode(= void *data, size_t size, return size ? NULL : patch; } =20 -static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci) +static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, + struct microcode_intel *mc, + u32 *cur_rev) { - struct microcode_intel *mc; - u32 rev, old_rev, date; + u32 rev; =20 - mc =3D uci->mc; if (!mc) return UCODE_NFOUND; =20 @@ -321,14 +321,12 @@ static enum ucode_state apply_microcode_early(struct = ucode_cpu_info *uci) * operation - when the other hyperthread has updated the microcode * already. */ - rev =3D intel_get_microcode_revision(); - if (rev >=3D mc->hdr.rev) { - uci->cpu_sig.rev =3D rev; + *cur_rev =3D intel_get_microcode_revision(); + if (*cur_rev >=3D mc->hdr.rev) { + uci->cpu_sig.rev =3D *cur_rev; return UCODE_OK; } =20 - old_rev =3D rev; - /* * Writeback and invalidate caches before updating microcode to avoid * internal issues depending on what the microcode is updating. @@ -343,13 +341,24 @@ static enum ucode_state apply_microcode_early(struct = ucode_cpu_info *uci) return UCODE_ERROR; =20 uci->cpu_sig.rev =3D rev; - - date =3D mc->hdr.date; - pr_info_once("updated early: 0x%x -> 0x%x, date =3D %04x-%02x-%02x\n", - old_rev, rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); return UCODE_UPDATED; } =20 +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci) +{ + struct microcode_intel *mc =3D uci->mc; + enum ucode_state ret; + u32 cur_rev, date; + + ret =3D __apply_microcode(uci, mc, &cur_rev); + if (ret =3D=3D UCODE_UPDATED) { + date =3D mc->hdr.date; + pr_info_once("updated early: 0x%x -> 0x%x, date =3D %04x-%02x-%02x\n", + cur_rev, mc->hdr.rev, date & 0xffff, date >> 24, (date >> 16) & 0x= ff); + } + return ret; +} + static __init bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax =3D 1, ebx, ecx =3D 0, edx; @@ -459,70 +468,29 @@ static int collect_cpu_info(int cpu_num, struct cpu_s= ignature *csig) return 0; } =20 -static enum ucode_state apply_microcode_intel(int cpu) +static enum ucode_state apply_microcode_late(int cpu) { struct ucode_cpu_info *uci =3D ucode_cpu_info + cpu; - struct cpuinfo_x86 *c =3D &cpu_data(cpu); - bool bsp =3D c->cpu_index =3D=3D boot_cpu_data.cpu_index; - struct microcode_intel *mc; + struct microcode_intel *mc =3D ucode_patch_late; enum ucode_state ret; - static int prev_rev; - u32 rev; + u32 cur_rev; =20 - /* We should bind the task to the CPU */ - if (WARN_ON(raw_smp_processor_id() !=3D cpu)) + if (WARN_ON_ONCE(smp_processor_id() !=3D cpu)) return UCODE_ERROR; =20 - mc =3D ucode_patch_late; - if (!mc) - return UCODE_NFOUND; + ret =3D __apply_microcode(uci, mc, &cur_rev); + if (ret !=3D UCODE_UPDATED && ret !=3D UCODE_OK) + return ret; =20 - /* - * Save us the MSR write below - which is a particular expensive - * operation - when the other hyperthread has updated the microcode - * already. - */ - rev =3D intel_get_microcode_revision(); - if (rev >=3D mc->hdr.rev) { - ret =3D UCODE_OK; - goto out; - } - - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - - /* write microcode via MSR 0x79 */ - wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); - - rev =3D intel_get_microcode_revision(); - - if (rev !=3D mc->hdr.rev) { - pr_err("CPU%d update to revision 0x%x failed\n", - cpu, mc->hdr.rev); - return UCODE_ERROR; - } - - if (bsp && rev !=3D prev_rev) { - pr_info("updated to revision 0x%x, date =3D %04x-%02x-%02x\n", - rev, - mc->hdr.date & 0xffff, - mc->hdr.date >> 24, + if (!cpu && uci->cpu_sig.rev !=3D cur_rev) { + pr_info("Updated to revision 0x%x, date =3D %04x-%02x-%02x\n", + uci->cpu_sig.rev, mc->hdr.date & 0xffff, mc->hdr.date >> 24, (mc->hdr.date >> 16) & 0xff); - prev_rev =3D rev; } =20 - ret =3D UCODE_UPDATED; - -out: - uci->cpu_sig.rev =3D rev; - c->microcode =3D rev; - - /* Update boot_cpu_data's revision too, if we're on the BSP: */ - if (bsp) - boot_cpu_data.microcode =3D rev; + cpu_data(cpu).microcode =3D uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode =3D uci->cpu_sig.rev; =20 return ret; } @@ -663,7 +631,7 @@ static void finalize_late_load(int result) static struct microcode_ops microcode_intel_ops =3D { .request_microcode_fw =3D request_microcode_fw, .collect_cpu_info =3D collect_cpu_info, - .apply_microcode =3D apply_microcode_intel, + .apply_microcode =3D apply_microcode_late, .finalize_late_load =3D finalize_late_load, };