From nobody Tue Dec 16 20:15:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB46ECDB47E for ; Fri, 20 Oct 2023 11:39:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377352AbjJTLja (ORCPT ); Fri, 20 Oct 2023 07:39:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377324AbjJTLit (ORCPT ); Fri, 20 Oct 2023 07:38:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F5A81FCF; Fri, 20 Oct 2023 04:38:05 -0700 (PDT) Date: Fri, 20 Oct 2023 11:37:49 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697801869; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RbbVmtC97Gh59IigR5LX8rqgp4ho0CEL+8wIxUbPnvc=; b=2MFAWLqTDZo5/K0hjoa6l8vYn5V4lQuKKXfL5TLSLo2CTvnRTI3QIPUicfFn5EvAXgT2kp oU7oT/DeqHZVLanZe6m0F34C1Lq5K05fuay/ZdvPVUEljB6CSCvBHpcm2nUVQ7Ipe8nDsO SeOTFT10mMI/yTVgjKGBh4I5Lm0hQ1spINHpqwVQQpbtHqsWeZ31rDDAWEPb0/PxYW/2fH kUpK1zntOEH9uxuHDWZQwadNHdB1jMgmDZpyU00988meq9Jn4OwZmFAcgPC1UqG/+lu0Df wQXwGoeu//iEoaSqkI2RvUCV7jeAMvb9TdGIELoZzE1m1MStk8PeS+mJL4TsLg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697801869; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RbbVmtC97Gh59IigR5LX8rqgp4ho0CEL+8wIxUbPnvc=; b=1ow8fSGqfW13V+Z241pi1AkiEANayKfjNuNoJnvk5A8X4fmUwP+cdBko41wPF8PaFTTnNi wMHZ/J5GYg56R8Cw== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/microcode] x86/microcode: Provide new control functions Cc: Thomas Gleixner , "Borislav Petkov (AMD)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20231002115903.377922731@linutronix.de> References: <20231002115903.377922731@linutronix.de> MIME-Version: 1.0 Message-ID: <169780186923.3135.11355710871406104676.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/microcode branch of tip: Commit-ID: 1844a781fdfbcbff64bfa59bd71fc6a62fdcdac0 Gitweb: https://git.kernel.org/tip/1844a781fdfbcbff64bfa59bd71fc6a62= fdcdac0 Author: Thomas Gleixner AuthorDate: Mon, 02 Oct 2023 14:00:02 +02:00 Committer: Borislav Petkov (AMD) CommitterDate: Thu, 19 Oct 2023 15:58:39 +02:00 x86/microcode: Provide new control functions The current all in one code is unreadable and really not suited for adding future features like uniform loading with package or system scope. Provide a set of new control functions which split the handling of the primary and secondary CPUs. These will replace the current rendezvous all in one function in the next step. This is intentionally a separate change because diff makes an complete unreadable mess otherwise. So the flow separates the primary and the secondary CPUs into their own functions which use the control field in the per CPU ucode_ctrl struct. primary() secondary() wait_for_all() wait_for_all() apply_ucode() wait_for_release() release() apply_ucode() Signed-off-by: Thomas Gleixner Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20231002115903.377922731@linutronix.de --- arch/x86/kernel/cpu/microcode/core.c | 84 +++++++++++++++++++++++++++- 1 file changed, 84 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 001c004..1ff38f9 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -290,6 +290,90 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } =20 +static bool wait_for_ctrl(void) +{ + unsigned int timeout; + + for (timeout =3D 0; timeout < USEC_PER_SEC; timeout++) { + if (this_cpu_read(ucode_ctrl.ctrl) !=3D SCTRL_WAIT) + return true; + udelay(1); + if (!(timeout % 1000)) + touch_nmi_watchdog(); + } + return false; +} + +static __maybe_unused void load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu =3D this_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + /* Initial rendezvous to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1); + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return; + } + + /* + * Wait for primary threads to complete. If one of them hangs due + * to the update, there is no way out. This is non-recoverable + * because the CPU might hold locks or resources and confuse the + * scheduler, watchdogs etc. There is no way to safely evacuate the + * machine. + */ + if (!wait_for_ctrl()) + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + + /* + * If the primary succeeded then invoke the apply() callback, + * otherwise copy the state from the primary thread. + */ + if (this_cpu_read(ucode_ctrl.ctrl) =3D=3D SCTRL_APPLY) + ret =3D microcode_ops->apply_microcode(cpu); + else + ret =3D per_cpu(ucode_ctrl.result, ctrl_cpu); + + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); +} + +static __maybe_unused void load_primary(unsigned int cpu) +{ + struct cpumask *secondaries =3D topology_sibling_cpumask(cpu); + enum sibling_ctrl ctrl; + enum ucode_state ret; + unsigned int sibling; + + /* Initial rendezvous to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1); + return; + } + + ret =3D microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + + /* + * If the update was successful, let the siblings run the apply() + * callback. If not, tell them it's done. This also covers the + * case where the CPU has uniform loading at package or system + * scope implemented but does not advertise it. + */ + if (ret =3D=3D UCODE_UPDATED || ret =3D=3D UCODE_OK) + ctrl =3D SCTRL_APPLY; + else + ctrl =3D SCTRL_DONE; + + for_each_cpu(sibling, secondaries) { + if (sibling !=3D cpu) + per_cpu(ucode_ctrl.ctrl, sibling) =3D ctrl; + } +} + static int load_cpus_stopped(void *unused) { int cpu =3D smp_processor_id();