From nobody Tue Dec 16 13:47:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0811CDB483 for ; Fri, 13 Oct 2023 06:18:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229770AbjJMGSq (ORCPT ); Fri, 13 Oct 2023 02:18:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229487AbjJMGSo (ORCPT ); Fri, 13 Oct 2023 02:18:44 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 059F195; Thu, 12 Oct 2023 23:18:40 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39D5QBdh019114; Fri, 13 Oct 2023 06:16:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=0EPYWk4IwhOCYQ1pgrfFbQvW+yVr8t6t5DLq4w0hXPc=; b=LhUChhNThj8k8dKTAY5oatvuK39zjeHFmcIT8IvUO1u8NpsRNGrXVFNd2uAk7Nn4fYxE 6DVbxVM0XO80BDkdiAp1owSRfLfanTVMk0jadI3kjkbDDflgD4yFmTz8tQazBT5Eva2+ bx84RxXJK1QkHUzQaMOKDnS4NoswfTW2mdhFF31fM5PGTvQakOqs4fNP5I0d4PLzKoml EKP47bNk80O1gIof/ClorxfkfiU7rda7mj2o8Wk6HvLdgxCGUr0af6p3slhK3+A/ZeIJ chfp0Ga/ra3RQ9P3gDU/cmsi1CxtXtF5aE3Tkn9AovVlx1B3LUYJo5WSLyWLSuG/eH3g rw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3tpt0x0jtt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Oct 2023 06:16:48 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39D6Gls7013072 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Oct 2023 06:16:47 GMT Received: from hu-prashk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 12 Oct 2023 23:16:44 -0700 From: Prashanth K To: , CC: Greg Kroah-Hartman , Hongyu Xie , Mathias Nyman , , Hongyu Xie , Mathias Nyman , Prashanth K Subject: [v2] xhci: Keep interrupt disabled in initialization until host is running. Date: Fri, 13 Oct 2023 11:46:37 +0530 Message-ID: <1697177797-18070-1-git-send-email-quic_prashk@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ySQijNyn4aYPecja2s-uf06Fxv-ihIn_ X-Proofpoint-ORIG-GUID: ySQijNyn4aYPecja2s-uf06Fxv-ihIn_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-13_03,2023-10-12_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=648 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310130053 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hongyu Xie [ Upstream commit a808925075fb750804a60ff0710614466c396db4 ] irq is disabled in xhci_quiesce(called by xhci_halt, with bit:2 cleared in USBCMD register), but xhci_run(called by usb_add_hcd) re-enable it. It's possible that you will receive thousands of interrupt requests after initialization for 2.0 roothub. And you will get a lot of warning like, "xHCI dying, ignoring interrupt. Shouldn't IRQs be disabled?". This amount of interrupt requests will cause the entire system to freeze. This problem was first found on a device with ASM2142 host controller on it. [tidy up old code while moving it, reword header -Mathias] Cc: stable@kernel.org Signed-off-by: Hongyu Xie Signed-off-by: Mathias Nyman Link: https://lore.kernel.org/r/20220623111945.1557702-2-mathias.nyman@linu= x.intel.com Signed-off-by: Greg Kroah-Hartman Cc: # 5.15 Signed-off-by: Prashanth K --- v2: Added a missing newline to avoid merge conflicts in future. drivers/usb/host/xhci.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 541fe4d..0803f9b 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -607,8 +607,27 @@ static int xhci_init(struct usb_hcd *hcd) =20 static int xhci_run_finished(struct xhci_hcd *xhci) { + unsigned long flags; + u32 temp; + + /* + * Enable interrupts before starting the host (xhci 4.2 and 5.5.2). + * Protect the short window before host is running with a lock + */ + spin_lock_irqsave(&xhci->lock, flags); + + xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts"); + temp =3D readl(&xhci->op_regs->command); + temp |=3D (CMD_EIE); + writel(temp, &xhci->op_regs->command); + + xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter"); + temp =3D readl(&xhci->ir_set->irq_pending); + writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); + if (xhci_start(xhci)) { xhci_halt(xhci); + spin_unlock_irqrestore(&xhci->lock, flags); return -ENODEV; } xhci->shared_hcd->state =3D HC_STATE_RUNNING; @@ -619,6 +638,9 @@ static int xhci_run_finished(struct xhci_hcd *xhci) =20 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_run for USB3 roothub"); + + spin_unlock_irqrestore(&xhci->lock, flags); + return 0; } =20 @@ -667,19 +689,6 @@ int xhci_run(struct usb_hcd *hcd) temp |=3D (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK; writel(temp, &xhci->ir_set->irq_control); =20 - /* Set the HCD state before we enable the irqs */ - temp =3D readl(&xhci->op_regs->command); - temp |=3D (CMD_EIE); - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Enable interrupts, cmd =3D 0x%x.", temp); - writel(temp, &xhci->op_regs->command); - - temp =3D readl(&xhci->ir_set->irq_pending); - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", - xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); - writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); - if (xhci->quirks & XHCI_NEC_HOST) { struct xhci_command *command; =20 --=20 2.7.4