From nobody Fri Jan 2 13:28:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E1B1CD6E51 for ; Wed, 11 Oct 2023 09:23:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231195AbjJKJXx (ORCPT ); Wed, 11 Oct 2023 05:23:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230351AbjJKJXv (ORCPT ); Wed, 11 Oct 2023 05:23:51 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 045E391; Wed, 11 Oct 2023 02:23:50 -0700 (PDT) Date: Wed, 11 Oct 2023 09:23:47 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697016228; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=poaexBJUv5tu6Pccgx/fYMMioEDwrLiYM+aMqFLGujY=; b=I5mk5tc4rhfKWaTKbJbVwrme7b6ip/Rw3Wyx5dl4zHCh1wy3a/nt8h2TpvT0vRyqhdVxnu 0TGK8iV6a1T8ggh7kmGE254V99aHZZdMEAFYcLyKvpgRhQOqcs9NWJYuGcPxkDh5akO0lB MfMyr23TSmKzQF56VaKh1UXw7ndudZUiZbanw9vnDceqStLwU2m4ysllm68fzDvorJmaVd CrF9PUAyR6HzCggouTOr6bZ63Ii32LJ3qbsQN/EwrcNZHykBGBaA0LhD5SMxElNqxi0Neb EerSXjolMegquXE2uVy/NAH2IHLViKNkbJ94pizU5xly8+TmKQQq1BvtoBXlag== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697016228; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=poaexBJUv5tu6Pccgx/fYMMioEDwrLiYM+aMqFLGujY=; b=1NxAwDFMIjeExXeJ+w3tuQ83drBiocue8T3hcUht4eEofmL6GoV7rjjQyCXUDXvsl76yd1 17q4UZ8BETr5pEBQ== From: "tip-bot2 for Borislav Petkov (AMD)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs Cc: rene@exactcode.de, "Borislav Petkov (AMD)" , , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: References: MIME-Version: 1.0 Message-ID: <169701622768.3135.17489375930381616520.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/urgent branch of tip: Commit-ID: f454b18e07f518bcd0c05af17a2239138bff52de Gitweb: https://git.kernel.org/tip/f454b18e07f518bcd0c05af17a2239138= bff52de Author: Borislav Petkov (AMD) AuthorDate: Sat, 07 Oct 2023 12:57:02 +02:00 Committer: Borislav Petkov (AMD) CommitterDate: Wed, 11 Oct 2023 11:00:11 +02:00 x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs Fix erratum #1485 on Zen4 parts where running with STIBP disabled can cause an #UD exception. The performance impact of the fix is negligible. Reported-by: Ren=C3=A9 Rebe Signed-off-by: Borislav Petkov (AMD) Tested-by: Ren=C3=A9 Rebe Cc: Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactc= ode.com --- arch/x86/include/asm/msr-index.h | 9 +++++++-- arch/x86/kernel/cpu/amd.c | 8 ++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 1d11135..b37abb5 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -637,12 +637,17 @@ /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e =20 -/* Fam 17h MSRs */ -#define MSR_F17H_IRPERF 0xc00000e9 +/* Zen4 */ +#define MSR_ZEN4_BP_CFG 0xc001102e +#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 =20 +/* Zen 2 */ #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) =20 +/* Fam 17h MSRs */ +#define MSR_F17H_IRPERF 0xc00000e9 + /* Fam 16h MSRs */ #define MSR_F16H_L2I_PERF_CTL 0xc0010230 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 03ef962..ece2b5b 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -80,6 +80,10 @@ static const int amd_div0[] =3D AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf), AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf)); =20 +static const int amd_erratum_1485[] =3D + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf), + AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf)); + static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratu= m) { int osvw_id =3D *erratum++; @@ -1149,6 +1153,10 @@ static void init_amd(struct cpuinfo_x86 *c) pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protect= ion.\n"); setup_force_cpu_bug(X86_BUG_DIV0); } + + if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && + cpu_has_amd_erratum(c, amd_erratum_1485)) + msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); } =20 #ifdef CONFIG_X86_32