From nobody Fri Jan 2 15:45:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8F6CCD68FE for ; Tue, 10 Oct 2023 08:19:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442734AbjJJITh (ORCPT ); Tue, 10 Oct 2023 04:19:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379439AbjJJITc (ORCPT ); Tue, 10 Oct 2023 04:19:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4693A4; Tue, 10 Oct 2023 01:19:31 -0700 (PDT) Date: Tue, 10 Oct 2023 08:19:29 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696925970; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=krtUQmSlb1m09HhIcJ/jP6C/QflQUzkrmaItwHGMfRw=; b=3sXeHpwlc19ZTlBI0oUOX1Bnchba2FKam4Y4CufzIZAwn91tXUtH2YRKq05x2pQubiLp4j giT/fVegzriMsKAUYsuucpcUkJV2hQKPPxOCpY3i/3J6E1RYVAt9Tkwu1MPKyeaCJ43vB3 2BB1oUQL+00hJvWY1kOn4Uq/y1i7hsEAG7AIUykwpGjDDukL2fwjBsk44sbVObOHI436Pb PKC4NNfUxJyE9XZ09v5Sr0fwBBMH+pBNxU0SUABy1HviL7D7R32jIZBEVjSMb18oO6GjQc EmzB7D3pVVBNAQSJUUuZrmen6A9InUcqeil4ev6CYlmY7cpsHFPi/7Ieh6ZMpQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696925970; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=krtUQmSlb1m09HhIcJ/jP6C/QflQUzkrmaItwHGMfRw=; b=jdmnkk8ZRGYQyG/pdN4qz8w93+ChYACpLYnI8nP2FTVsbv5rF7s5FLDN4dkecMVst0WONS YPLBBZ8I7bPWwoBw== From: "tip-bot2 for Sandipan Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/amd/uncore: Use rdmsr if rdpmc is unavailable Cc: Sandipan Das , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: =?utf-8?q?=3Ce9d994e32a3fcb39fa59fcf43ab4260d11aba097=2E16964?= =?utf-8?q?25185=2Egit=2Esandipan=2Edas=40amd=2Ecom=3E?= References: =?utf-8?q?=3Ce9d994e32a3fcb39fa59fcf43ab4260d11aba097=2E169642?= =?utf-8?q?5185=2Egit=2Esandipan=2Edas=40amd=2Ecom=3E?= MIME-Version: 1.0 Message-ID: <169692596934.3135.13596342947023817018.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 7ef0343855dc23a979a53b3143540f93f3e5bef8 Gitweb: https://git.kernel.org/tip/7ef0343855dc23a979a53b3143540f93f= 3e5bef8 Author: Sandipan Das AuthorDate: Thu, 05 Oct 2023 10:53:13 +05:30 Committer: Peter Zijlstra CommitterDate: Mon, 09 Oct 2023 16:12:24 +02:00 perf/x86/amd/uncore: Use rdmsr if rdpmc is unavailable Not all uncore PMUs may support the use of the RDPMC instruction for reading counters. In such cases, read the count from the corresponding PERF_CTR register using the RDMSR instruction. Signed-off-by: Sandipan Das Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/e9d994e32a3fcb39fa59fcf43ab4260d11aba097.16= 96425185.git.sandipan.das@amd.com --- arch/x86/events/amd/uncore.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index ff1d09c..2fe6239 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -96,7 +96,16 @@ static void amd_uncore_read(struct perf_event *event) */ =20 prev =3D local64_read(&hwc->prev_count); - rdpmcl(hwc->event_base_rdpmc, new); + + /* + * Some uncore PMUs do not have RDPMC assignments. In such cases, + * read counts directly from the corresponding PERF_CTR. + */ + if (hwc->event_base_rdpmc < 0) + rdmsrl(hwc->event_base, new); + else + rdpmcl(hwc->event_base_rdpmc, new); + local64_set(&hwc->prev_count, new); delta =3D (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); delta >>=3D COUNTER_SHIFT; @@ -164,6 +173,9 @@ out: hwc->event_base_rdpmc =3D pmu->rdpmc_base + hwc->idx; hwc->state =3D PERF_HES_UPTODATE | PERF_HES_STOPPED; =20 + if (pmu->rdpmc_base < 0) + hwc->event_base_rdpmc =3D -1; + if (flags & PERF_EF_START) event->pmu->start(event, PERF_EF_RELOAD);