From nobody Fri Jan 2 22:08:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E74B4E95A61 for ; Sat, 7 Oct 2023 12:01:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343933AbjJGMBP (ORCPT ); Sat, 7 Oct 2023 08:01:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343911AbjJGMAw (ORCPT ); Sat, 7 Oct 2023 08:00:52 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63BC0B6 for ; Sat, 7 Oct 2023 05:00:50 -0700 (PDT) Date: Sat, 07 Oct 2023 12:00:48 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696680049; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YYLHC9U7kPuDfxsDlF3mapnm6QhMu14KdRfEE+aGdgA=; b=w8igbKe1kw/SVi3G8hzZL3eY3CPh3eK7iBeLJVJQeRxoebISblPFcqMi+OJgfKsX4cDE3c ZRGvymfixgLPu3PPDgUC8be5I5U/7OC3Ke2u4E5zcR5eR27wVE32BlrioEQVr72WsGC8mG pbkBFP59hnKdsd5btKfuJXnRCMdcGftnhH/yQq1xDeJn/xiokA18J51TC4oi6Hv+wMU8eR G8qzPnexg+imMVWVNhqMHovcDF48O3mkV/l7IksleA7NVUEDmglYA/WFoA8XPg8oxe52i/ GGUKmOmvS0V4ddAc03iRau2qHbf+dSt/tCc8gdozfC0AIoIFF1rkTPpLQOUwYQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696680049; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YYLHC9U7kPuDfxsDlF3mapnm6QhMu14KdRfEE+aGdgA=; b=Lv6dp0l/qgZJW+2kyi/s7n6nDF5qM8uVvHjLiH2QTMwNHvGoLhKxl2F33+kvc57mOZt7AB BqYZHbBWUDaoMfAw== From: "irqchip-bot for Lad Prabhakar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-fixes] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC Cc: Lad Prabhakar , Rob Herring , Geert Uytterhoeven , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20231006121058.13890-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20231006121058.13890-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Message-ID: <169668004801.3135.16099929262408472906.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-fixes branch of i= rqchip: Commit-ID: db712c0089bd8e9e47c286ed772d86fb187d0854 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/db712c0089bd8e9e47c286ed772d86fb187d0854 Author: Lad Prabhakar AuthorDate: Fri, 06 Oct 2023 13:10:58 +01:00 Committer: Marc Zyngier CommitterDate: Sat, 07 Oct 2023 12:27:39 +01:00 dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC the only difference being it can support BUS_ERR_INT for which it has additional registers. Hence new generic compatible string "renesas,r9a07g043u-irqc" is added for RZ/G2UL SoC. Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC interrupt-names property is added so that we can parse them based on names. While at it updated the example node to four spaces and added interrupt-names property. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20231006121058.13890-1-prabhakar.mahadev-la= d.rj@bp.renesas.com --- Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.= yaml | 225 ++++++++++++++++++++++++++++++++++++++++++++++++++++------------= ------ 1 file changed, 170 insertions(+), 55 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/r= enesas,rzg2l-irqc.yaml index ea7db36..2ef3081 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml @@ -19,13 +19,11 @@ description: | - NMI edge select (NMI is not treated as NMI exception and supports fa= ll edge and stand-up edge detection interrupts) =20 -allOf: - - $ref: /schemas/interrupt-controller.yaml# - properties: compatible: items: - enum: + - renesas,r9a07g043u-irqc # RZ/G2UL - renesas,r9a07g044-irqc # RZ/G2{L,LC} - renesas,r9a07g054-irqc # RZ/V2L - const: renesas,rzg2l-irqc @@ -45,7 +43,96 @@ properties: maxItems: 1 =20 interrupts: - maxItems: 41 + minItems: 41 + items: + - description: NMI interrupt + - description: IRQ0 interrupt + - description: IRQ1 interrupt + - description: IRQ2 interrupt + - description: IRQ3 interrupt + - description: IRQ4 interrupt + - description: IRQ5 interrupt + - description: IRQ6 interrupt + - description: IRQ7 interrupt + - description: GPIO interrupt, TINT0 + - description: GPIO interrupt, TINT1 + - description: GPIO interrupt, TINT2 + - description: GPIO interrupt, TINT3 + - description: GPIO interrupt, TINT4 + - description: GPIO interrupt, TINT5 + - description: GPIO interrupt, TINT6 + - description: GPIO interrupt, TINT7 + - description: GPIO interrupt, TINT8 + - description: GPIO interrupt, TINT9 + - description: GPIO interrupt, TINT10 + - description: GPIO interrupt, TINT11 + - description: GPIO interrupt, TINT12 + - description: GPIO interrupt, TINT13 + - description: GPIO interrupt, TINT14 + - description: GPIO interrupt, TINT15 + - description: GPIO interrupt, TINT16 + - description: GPIO interrupt, TINT17 + - description: GPIO interrupt, TINT18 + - description: GPIO interrupt, TINT19 + - description: GPIO interrupt, TINT20 + - description: GPIO interrupt, TINT21 + - description: GPIO interrupt, TINT22 + - description: GPIO interrupt, TINT23 + - description: GPIO interrupt, TINT24 + - description: GPIO interrupt, TINT25 + - description: GPIO interrupt, TINT26 + - description: GPIO interrupt, TINT27 + - description: GPIO interrupt, TINT28 + - description: GPIO interrupt, TINT29 + - description: GPIO interrupt, TINT30 + - description: GPIO interrupt, TINT31 + - description: Bus error interrupt + + interrupt-names: + minItems: 41 + items: + - const: nmi + - const: irq0 + - const: irq1 + - const: irq2 + - const: irq3 + - const: irq4 + - const: irq5 + - const: irq6 + - const: irq7 + - const: tint0 + - const: tint1 + - const: tint2 + - const: tint3 + - const: tint4 + - const: tint5 + - const: tint6 + - const: tint7 + - const: tint8 + - const: tint9 + - const: tint10 + - const: tint11 + - const: tint12 + - const: tint13 + - const: tint14 + - const: tint15 + - const: tint16 + - const: tint17 + - const: tint18 + - const: tint19 + - const: tint20 + - const: tint21 + - const: tint22 + - const: tint23 + - const: tint24 + - const: tint25 + - const: tint26 + - const: tint27 + - const: tint28 + - const: tint29 + - const: tint30 + - const: tint31 + - const: bus-err =20 clocks: maxItems: 2 @@ -73,6 +160,23 @@ required: - power-domains - resets =20 +allOf: + - $ref: /schemas/interrupt-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043u-irqc + then: + properties: + interrupts: + minItems: 42 + interrupt-names: + minItems: 42 + required: + - interrupt-names + unevaluatedProperties: false =20 examples: @@ -81,55 +185,66 @@ examples: #include =20 irqc: interrupt-controller@110a0000 { - compatible =3D "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; - reg =3D <0x110a0000 0x10000>; - #interrupt-cells =3D <2>; - #address-cells =3D <0>; - interrupt-controller; - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks =3D <&cpg CPG_MOD R9A07G044_IA55_CLK>, - <&cpg CPG_MOD R9A07G044_IA55_PCLK>; - clock-names =3D "clk", "pclk"; - power-domains =3D <&cpg>; - resets =3D <&cpg R9A07G044_IA55_RESETN>; + compatible =3D "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; + reg =3D <0x110a0000 0x10000>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31"; + clocks =3D <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names =3D "clk", "pclk"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G044_IA55_RESETN>; };