From nobody Wed Dec 17 08:26:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 480BCE743C2 for ; Thu, 28 Sep 2023 21:11:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232344AbjI1VLv (ORCPT ); Thu, 28 Sep 2023 17:11:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232416AbjI1VLr (ORCPT ); Thu, 28 Sep 2023 17:11:47 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03AFECD7; Thu, 28 Sep 2023 14:11:44 -0700 (PDT) Date: Thu, 28 Sep 2023 21:11:43 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1695935503; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U2Te0Ehq1sOf3rHkrQLmrN1+rshPRVWPdcTNxhnaR3c=; b=gbmBwInlV4KweySF5R8dtYpzqdbbmgb3MYwV/OyCcqSIUgBDudqomquWO0mfNGwcfQqto1 fvso8U3K36pXJJhQ7DcWXztQsIoBiVtf1W5JmEL4ghb9sGVxTJqotj8uTe/m3vf5KcXiJ9 YPN7V0+l7Yhehjg5JC22/2TzIxeqTg+Wjki/tRfPOHl8G+/EX/hmFQnj2u4fzaqW/zq7gV jI6kMzvORnI6by55/OsCarEEBFXH59zdGouLhg+AV6yNmPR4ZtCmjbbYzlp8F+uvp8451x WBS+0KTuLtwDqPP2ed/OoOTTEin4QeVXyIMPxVv9h0q5qTSZhixJb0rkPsmRMg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1695935503; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U2Te0Ehq1sOf3rHkrQLmrN1+rshPRVWPdcTNxhnaR3c=; b=4PkkHED72mxpiOppzEPfjnGajLJVOMismn6k4NrjKT8Wuq/WOqpEyDlM8uUDD5JjCHBBzt u8xOVOIUxswp9dCg== From: "tip-bot2 for Adam Dunlap" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/mm] x86/sev-es: Set x86_virt_bits to the correct value straight away, instead of a two-phase approach Cc: Dave Hansen , Adam Dunlap , Ingo Molnar , Jacob Xu , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230912002703.3924521-3-acdunlap@google.com> References: <20230912002703.3924521-3-acdunlap@google.com> MIME-Version: 1.0 Message-ID: <169593550300.27769.9551262175239448293.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/mm branch of tip: Commit-ID: fbf6449f84bf5e4ad09f2c09ee70ed7d629b5ff6 Gitweb: https://git.kernel.org/tip/fbf6449f84bf5e4ad09f2c09ee70ed7d6= 29b5ff6 Author: Adam Dunlap AuthorDate: Mon, 11 Sep 2023 17:27:03 -07:00 Committer: Ingo Molnar CommitterDate: Thu, 28 Sep 2023 22:49:35 +02:00 x86/sev-es: Set x86_virt_bits to the correct value straight away, instead o= f a two-phase approach Instead of setting x86_virt_bits to a possibly-correct value and then correcting it later, do all the necessary checks before setting it. At this point, the #VC handler references boot_cpu_data.x86_virt_bits, and in the previous version, it would be triggered by the CPUIDs between the point at which it is set to 48 and when it is set to the correct value. Suggested-by: Dave Hansen Signed-off-by: Adam Dunlap Signed-off-by: Ingo Molnar Tested-by: Jacob Xu Link: https://lore.kernel.org/r/20230912002703.3924521-3-acdunlap@google.com --- arch/x86/kernel/cpu/common.c | 37 ++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 382d4e6..8d7063e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1114,17 +1114,32 @@ void get_cpu_cap(struct cpuinfo_x86 *c) void get_cpu_address_sizes(struct cpuinfo_x86 *c) { u32 eax, ebx, ecx, edx; + bool vp_bits_from_cpuid =3D true; =20 - if (c->extended_cpuid_level >=3D 0x80000008) { + if (!cpu_has(c, X86_FEATURE_CPUID) || + (c->extended_cpuid_level < 0x80000008)) + vp_bits_from_cpuid =3D false; + + if (vp_bits_from_cpuid) { cpuid(0x80000008, &eax, &ebx, &ecx, &edx); =20 c->x86_virt_bits =3D (eax >> 8) & 0xff; c->x86_phys_bits =3D eax & 0xff; + } else { + if (IS_ENABLED(CONFIG_X86_64)) { + c->x86_clflush_size =3D 64; + c->x86_phys_bits =3D 36; + c->x86_virt_bits =3D 48; + } else { + c->x86_clflush_size =3D 32; + c->x86_virt_bits =3D 32; + c->x86_phys_bits =3D 32; + + if (cpu_has(c, X86_FEATURE_PAE) || + cpu_has(c, X86_FEATURE_PSE36)) + c->x86_phys_bits =3D 36; + } } -#ifdef CONFIG_X86_32 - else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) - c->x86_phys_bits =3D 36; -#endif c->x86_cache_bits =3D c->x86_phys_bits; } =20 @@ -1579,15 +1594,6 @@ static void __init cpu_parse_early_param(void) */ static void __init early_identify_cpu(struct cpuinfo_x86 *c) { -#ifdef CONFIG_X86_64 - c->x86_clflush_size =3D 64; - c->x86_phys_bits =3D 36; - c->x86_virt_bits =3D 48; -#else - c->x86_clflush_size =3D 32; - c->x86_phys_bits =3D 32; - c->x86_virt_bits =3D 32; -#endif c->x86_cache_alignment =3D c->x86_clflush_size; =20 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); @@ -1601,7 +1607,6 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) cpu_detect(c); get_cpu_vendor(c); get_cpu_cap(c); - get_cpu_address_sizes(c); setup_force_cpu_cap(X86_FEATURE_CPUID); cpu_parse_early_param(); =20 @@ -1617,6 +1622,8 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) setup_clear_cpu_cap(X86_FEATURE_CPUID); } =20 + get_cpu_address_sizes(c); + setup_force_cpu_cap(X86_FEATURE_ALWAYS); =20 cpu_set_bug_bits(c);