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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099E2.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6792.11 via Frontend Transport; Mon, 11 Sep 2023 19:25:42 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 11 Sep 2023 14:25:37 -0500 From: Sanjay R Mehta To: CC: , , , , , , , Sanjay R Mehta Subject: [PATCH 1/3] dmaengine: ae4dma: Initial ae4dma controller driver with multi channel Date: Mon, 11 Sep 2023 14:25:22 -0500 Message-ID: <1694460324-60346-2-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1694460324-60346-1-git-send-email-Sanju.Mehta@amd.com> References: <1694460324-60346-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|MN0PR12MB6101:EE_ X-MS-Office365-Filtering-Correlation-Id: 905c4ff9-5023-4d3e-8643-08dbb2fce3be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2023 19:25:42.4536 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 905c4ff9-5023-4d3e-8643-08dbb2fce3be X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6101 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sanjay R Mehta Add support for AMD AE4DMA controller. It performs high-bandwidth memory to memory and IO copy operation. Device commands are managed via a circular queue of 'descriptors', each of which specifies source and destination addresses for copying a single buffer of data. Signed-off-by: Sanjay R Mehta --- MAINTAINERS | 6 + drivers/dma/Kconfig | 2 + drivers/dma/Makefile | 1 + drivers/dma/ae4dma/Kconfig | 11 ++ drivers/dma/ae4dma/Makefile | 10 ++ drivers/dma/ae4dma/ae4dma-dev.c | 320 +++++++++++++++++++++++++++++++++++++ drivers/dma/ae4dma/ae4dma-pci.c | 247 +++++++++++++++++++++++++++++ drivers/dma/ae4dma/ae4dma.h | 338 ++++++++++++++++++++++++++++++++++++= ++++ 8 files changed, 935 insertions(+) create mode 100644 drivers/dma/ae4dma/Kconfig create mode 100644 drivers/dma/ae4dma/Makefile create mode 100644 drivers/dma/ae4dma/ae4dma-dev.c create mode 100644 drivers/dma/ae4dma/ae4dma-pci.c create mode 100644 drivers/dma/ae4dma/ae4dma.h diff --git a/MAINTAINERS b/MAINTAINERS index d590ce3..fdcc6d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -891,6 +891,12 @@ Q: https://patchwork.kernel.org/project/linux-rdma/lis= t/ F: drivers/infiniband/hw/efa/ F: include/uapi/rdma/efa-abi.h =20 +AMD AE4DMA DRIVER +M: Sanjay R Mehta +L: dmaengine@vger.kernel.org +S: Maintained +F: drivers/dma/ae4dma/ + AMD CDX BUS DRIVER M: Nipun Gupta M: Nikhil Agarwal diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 08fdd0e..b26dbfb 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -777,6 +777,8 @@ source "drivers/dma/fsl-dpaa2-qdma/Kconfig" =20 source "drivers/dma/lgm/Kconfig" =20 +source "drivers/dma/ae4dma/Kconfig" + # clients comment "DMA Clients" depends on DMA_ENGINE diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index a4fd1ce..513d87f 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_XGENE_DMA) +=3D xgene-dma.o obj-$(CONFIG_ST_FDMA) +=3D st_fdma.o obj-$(CONFIG_FSL_DPAA2_QDMA) +=3D fsl-dpaa2-qdma/ obj-$(CONFIG_INTEL_LDMA) +=3D lgm/ +obj-$(CONFIG_AMD_AE4DMA) +=3D ae4dma/ =20 obj-y +=3D mediatek/ obj-y +=3D qcom/ diff --git a/drivers/dma/ae4dma/Kconfig b/drivers/dma/ae4dma/Kconfig new file mode 100644 index 0000000..1cda9de --- /dev/null +++ b/drivers/dma/ae4dma/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +config AMD_AE4DMA + tristate "AMD AE4DMA Engine" + depends on X86_64 && PCI + help + Enabling this option provides support for the AMD AE4DMA controller, + which offers DMA capabilities for high-bandwidth memory-to-memory and + I/O copy operations. The controller utilizes a queue-based descriptor + management system for efficient DMA transfers. It is specifically + designed to be used in conjunction with AMD Non-Transparent Bridge devi= ces + and is not intended for general-purpose peripheral DMA functionality. diff --git a/drivers/dma/ae4dma/Makefile b/drivers/dma/ae4dma/Makefile new file mode 100644 index 0000000..db9cab1 --- /dev/null +++ b/drivers/dma/ae4dma/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# AMD AE4DMA driver +# + +obj-$(CONFIG_AMD_AE4DMA) +=3D ae4dma.o + +ae4dma-objs :=3D ae4dma-dev.o + +ae4dma-$(CONFIG_PCI) +=3D ae4dma-pci.o diff --git a/drivers/dma/ae4dma/ae4dma-dev.c b/drivers/dma/ae4dma/ae4dma-de= v.c new file mode 100644 index 0000000..a3c50a2 --- /dev/null +++ b/drivers/dma/ae4dma/ae4dma-dev.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD AE4DMA device driver + * -- Based on the PTDMA driver + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Sanjay R Mehta + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ae4dma.h" +#include "../dmaengine.h" +#include "../virt-dma.h" + +static unsigned int max_hw_q =3D 1; +module_param(max_hw_q, uint, 0444); +MODULE_PARM_DESC(max_hw_q, "Max queues per engine (any non-zero value less= than or equal to 16, default: 1)"); + +/* Human-readable error strings */ +static char *ae4_error_codes[] =3D { + "", + "ERR 01: INVALID HEADER DW0", + "ERR 02: INVALID STATUS", + "ERR 03: INVALID LENGTH - 4 BYTE ALIGNMENT", + "ERR 04: INVALID SRC ADDR - 4 BYTE ALIGNMENT", + "ERR 05: INVALID DST ADDR - 4 BYTE ALIGNMENT", + "ERR 06: INVALID ALIGNMENT", + "ERR 07: INVALID DESCRIPTOR", +}; + +static void ae4_log_error(struct ae4_device *d, int e) +{ + if (e <=3D 7) + dev_info(d->dev, "AE4DMA error: %s (0x%x)\n", ae4_error_codes[e], e); + else if (e > 7 && e <=3D 15) + dev_info(d->dev, "AE4DMA error: %s (0x%x)\n", "INVALID DESCRIPTOR", e); + else if (e > 15 && e <=3D 31) + dev_info(d->dev, "AE4DMA error: %s (0x%x)\n", "INVALID DESCRIPTOR", e); + else if (e > 31 && e <=3D 63) + dev_info(d->dev, "AE4DMA error: %s (0x%x)\n", "INVALID DESCRIPTOR", e); + else if (e > 63 && e <=3D 127) + dev_info(d->dev, "AE4DMA error: %s (0x%x)\n", "PTE ERROR", e); + else if (e > 127 && e <=3D 255) + dev_info(d->dev, "AE4DMA error: %s (0x%x)\n", "PTE ERROR", e); +} + +void ae4_start_queue(struct ae4_cmd_queue *cmd_q) +{ + /* Turn on the run bit */ + iowrite32(cmd_q->qcontrol | CMD_Q_RUN, cmd_q->reg_control); +} + +void ae4_stop_queue(struct ae4_cmd_queue *cmd_q) +{ + /* Turn off the run bit */ + iowrite32(cmd_q->qcontrol & ~CMD_Q_RUN, cmd_q->reg_control); +} + +static int ae4_core_execute_cmd(struct ae4dma_desc *desc, struct ae4_cmd_q= ueue *cmd_q) +{ + bool soc =3D FIELD_GET(DWORD0_SOC, desc->dw0); + u8 *q_desc =3D (u8 *)&cmd_q->qbase[0]; + u32 tail_wi; + + cmd_q->int_rcvd =3D 0; + + if (soc) { + desc->dw0 |=3D FIELD_PREP(DWORD0_IOC, desc->dw0); + desc->dw0 &=3D ~DWORD0_SOC; + } + mutex_lock(&cmd_q->q_mutex); + + /* Write Index of circular queue */ + tail_wi =3D ioread32(cmd_q->reg_control + 0x10); + q_desc +=3D (tail_wi * 32); + + /* Copy 32-byte command descriptor to hw queue. */ + memcpy(q_desc, desc, 32); + cmd_q->qidx =3D (cmd_q->qidx + 1) % CMD_Q_LEN; // Increment q_desc id. + + /* The data used by this command must be flushed to memory */ + wmb(); + + /* Write the new tail_wi address back to the queue register */ + tail_wi =3D (tail_wi + 1) % CMD_Q_LEN; + iowrite32(tail_wi, cmd_q->reg_control + 0x10); + + mutex_unlock(&cmd_q->q_mutex); + + return 0; +} + +int ae4_core_perform_passthru(struct ae4_cmd_queue *cmd_q, struct ae4_pass= thru_engine *ae4_engine) +{ + struct ae4dma_desc desc; + struct ae4_device *ae4 =3D cmd_q->ae4; + + cmd_q->cmd_error =3D 0; + memset(&desc, 0, sizeof(desc)); + desc.dw0 =3D CMD_DESC_DW0_VAL; + desc.dw1.status =3D 0; + desc.dw1.err_code =3D 0; + desc.dw1.desc_id =3D 0; + desc.length =3D ae4_engine->src_len; + desc.src_lo =3D upper_32_bits(ae4_engine->src_dma); + desc.src_hi =3D lower_32_bits(ae4_engine->src_dma); + desc.dst_lo =3D upper_32_bits(ae4_engine->dst_dma); + desc.dst_hi =3D lower_32_bits(ae4_engine->dst_dma); + + if (cmd_q->int_en) + ae4_core_enable_queue_interrupts(ae4, cmd_q); + else + ae4_core_disable_queue_interrupts(ae4, cmd_q); + + return ae4_core_execute_cmd(&desc, cmd_q); +} + +static void ae4_do_cmd_complete(struct tasklet_struct *t) +{ + struct ae4_cmd_queue *cmd_q =3D from_tasklet(cmd_q, t, irq_tasklet); + unsigned long flags; + struct ae4_cmd *cmd; + + spin_lock_irqsave(&cmd_q->cmd_lock, flags); + cmd =3D list_first_entry(&cmd_q->cmd, struct ae4_cmd, entry); + list_del(&cmd->entry); + spin_unlock_irqrestore(&cmd_q->cmd_lock, flags); + + cmd->ae4_cmd_callback(cmd->data, cmd->ret); +} + +void ae4_check_status_trans(struct ae4_device *ae4, struct ae4_cmd_queue *= cmd_q) +{ + u8 status; + int head =3D ioread32(cmd_q->reg_control + 0x0C); + struct ae4dma_desc *desc; + + head =3D (head - 1) & (CMD_Q_LEN - 1); + desc =3D &cmd_q->qbase[head]; + + status =3D desc->dw1.status; + if (status) { + cmd_q->int_status =3D status; + if (status !=3D 0x3) { + /* On error, only save the first error value */ + cmd_q->cmd_error =3D desc->dw1.err_code; + if (cmd_q->cmd_error) { + /* + * Log the error and flush the queue by + * moving the head pointer + */ + ae4_log_error(cmd_q->ae4, cmd_q->cmd_error); + } + } + } +} + +static irqreturn_t ae4_core_irq_handler(int irq, void *data) +{ + struct ae4_cmd_queue *cmd_q =3D data; + struct ae4_device *ae4 =3D cmd_q->ae4; + u32 status =3D ioread32(cmd_q->reg_control + 0x4); + u8 q_intr_type =3D (status >> 24) & 0xf; + + if (q_intr_type =3D=3D 0x4) + dev_info(ae4->dev, "AE4DMA INTR: %s (0x%x)\n", "queue desc error", q_int= r_type); + else if (q_intr_type =3D=3D 0x2) + dev_info(ae4->dev, "AE4DMA INTR: %s (0x%x)\n", "queue stopped", q_intr_t= ype); + else if (q_intr_type =3D=3D 0x1) + dev_info(ae4->dev, "AE4DMA INTR: %s (0x%x)\n", "queue empty", q_intr_typ= e); + else + dev_info(ae4->dev, "AE4DMA INTR: %s (0x%x)\n", "unknown error", q_intr_t= ype); + + ae4_check_status_trans(ae4, cmd_q); + + tasklet_schedule(&cmd_q->irq_tasklet); + + return IRQ_HANDLED; +} + +int ae4_core_init(struct ae4_device *ae4) +{ + char dma_pool_name[MAX_DMAPOOL_NAME_LEN]; + struct ae4_cmd_queue *cmd_q; + u32 dma_addr_lo, dma_addr_hi; + struct device *dev =3D ae4->dev; + struct dma_pool *dma_pool; + unsigned int i; + int ret; + u32 q_per_eng =3D max_hw_q; + + /* Update the device registers with queue information. */ + iowrite32(q_per_eng, ae4->io_regs); + + q_per_eng =3D ioread32(ae4->io_regs); + + for (i =3D 0; i < q_per_eng; i++) { + /* Allocate a dma pool for the queue */ + snprintf(dma_pool_name, sizeof(dma_pool_name), "%s_q%d", dev_name(ae4->d= ev), i); + dma_pool =3D dma_pool_create(dma_pool_name, dev, + AE4_DMAPOOL_MAX_SIZE, + AE4_DMAPOOL_ALIGN, 0); + if (!dma_pool) + return -ENOMEM; + + /* ae4dma core initialisation */ + cmd_q =3D &ae4->cmd_q[i]; + cmd_q->id =3D ae4->cmd_q_count; + ae4->cmd_q_count++; + cmd_q->ae4 =3D ae4; + cmd_q->dma_pool =3D dma_pool; + mutex_init(&cmd_q->q_mutex); + spin_lock_init(&cmd_q->q_lock); + + /* Preset some register values (Q size is 32byte (0x20)) */ + cmd_q->reg_control =3D ae4->io_regs + ((i + 1) * 0x20); + + /* Page alignment satisfies our needs for N <=3D 128 */ + cmd_q->qsize =3D Q_SIZE(Q_DESC_SIZE); + cmd_q->qbase =3D dma_alloc_coherent(dev, cmd_q->qsize, &cmd_q->qbase_dma= , GFP_KERNEL); + + if (!cmd_q->qbase) { + ret =3D -ENOMEM; + goto e_destroy_pool; + } + + cmd_q->qidx =3D 0; + cmd_q->q_space_available =3D 0; + + init_waitqueue_head(&cmd_q->int_queue); + init_waitqueue_head(&cmd_q->q_space); + + dev_dbg(dev, "queue #%u available\n", i); + } + + if (ae4->cmd_q_count =3D=3D 0) { + dev_notice(dev, "no command queues available\n"); + ret =3D -EIO; + goto e_destroy_pool; + } + for (i =3D 0; i < ae4->cmd_q_count; i++) { + cmd_q =3D &ae4->cmd_q[i]; + cmd_q->qcontrol =3D 0; + ret =3D request_irq(ae4->ae4_irq[i], ae4_core_irq_handler, 0, + dev_name(ae4->dev), cmd_q); + if (ret) { + dev_err(dev, "unable to allocate an IRQ\n"); + goto e_free_dma; + } + + /* Update the device registers with cnd queue length (Max Index reg). */ + iowrite32(CMD_Q_LEN, cmd_q->reg_control + 0x08); + cmd_q->qdma_tail =3D cmd_q->qbase_dma; + dma_addr_lo =3D lower_32_bits(cmd_q->qdma_tail); + iowrite32((u32)dma_addr_lo, cmd_q->reg_control + 0x18); + dma_addr_lo =3D ioread32(cmd_q->reg_control + 0x18); + dma_addr_hi =3D upper_32_bits(cmd_q->qdma_tail); + iowrite32((u32)dma_addr_hi, cmd_q->reg_control + 0x1C); + dma_addr_hi =3D ioread32(cmd_q->reg_control + 0x1C); + ae4_core_enable_queue_interrupts(ae4, cmd_q); + INIT_LIST_HEAD(&cmd_q->cmd); + + /* Initialize the ISR tasklet */ + tasklet_setup(&cmd_q->irq_tasklet, ae4_do_cmd_complete); + } + + return 0; + +e_free_dma: + dma_free_coherent(dev, cmd_q->qsize, cmd_q->qbase, cmd_q->qbase_dma); + +e_destroy_pool: + for (i =3D 0; i < ae4->cmd_q_count; i++) + dma_pool_destroy(ae4->cmd_q[i].dma_pool); + + return ret; +} + +void ae4_core_destroy(struct ae4_device *ae4) +{ + struct device *dev =3D ae4->dev; + struct ae4_cmd_queue *cmd_q; + struct ae4_cmd *cmd; + unsigned int i; + + for (i =3D 0; i < ae4->cmd_q_count; i++) { + cmd_q =3D &ae4->cmd_q[i]; + + wake_up_all(&cmd_q->q_space); + wake_up_all(&cmd_q->int_queue); + + /* Disable and clear interrupts */ + ae4_core_disable_queue_interrupts(ae4, cmd_q); + + /* Turn off the run bit */ + ae4_stop_queue(cmd_q); + + free_irq(ae4->ae4_irq[i], cmd_q); + + dma_free_coherent(dev, cmd_q->qsize, cmd_q->qbase, + cmd_q->qbase_dma); + } + + /* Flush the cmd queue */ + while (!list_empty(&ae4->cmd)) { + /* Invoke the callback directly with an error code */ + cmd =3D list_first_entry(&ae4->cmd, struct ae4_cmd, entry); + list_del(&cmd->entry); + cmd->ae4_cmd_callback(cmd->data, -ENODEV); + } +} diff --git a/drivers/dma/ae4dma/ae4dma-pci.c b/drivers/dma/ae4dma/ae4dma-pc= i.c new file mode 100644 index 0000000..a77fbb5 --- /dev/null +++ b/drivers/dma/ae4dma/ae4dma-pci.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD AE4DMA device driver + * -- Based on the PTDMA driver + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Sanjay R Mehta + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ae4dma.h" + +struct ae4_msix { + int msix_count; + struct msix_entry msix_entry[MAX_HW_QUEUES]; +}; + +/* + * ae4_alloc_struct - allocate and initialize the ae4_device struct + * + * @dev: device struct of the AE4DMA + */ +static struct ae4_device *ae4_alloc_struct(struct device *dev) +{ + struct ae4_device *ae4; + + ae4 =3D devm_kzalloc(dev, sizeof(*ae4), GFP_KERNEL); + + if (!ae4) + return NULL; + ae4->dev =3D dev; + + INIT_LIST_HEAD(&ae4->cmd); + + return ae4; +} + +static int ae4_get_msix_irqs(struct ae4_device *ae4) +{ + struct ae4_msix *ae4_msix =3D ae4->ae4_msix; + struct device *dev =3D ae4->dev; + struct pci_dev *pdev =3D to_pci_dev(dev); + int v, i, ret; + + for (v =3D 0; v < ARRAY_SIZE(ae4_msix->msix_entry); v++) + ae4_msix->msix_entry[v].entry =3D v; + + ret =3D pci_enable_msix_range(pdev, ae4_msix->msix_entry, 1, v); + if (ret < 0) + return ret; + + ae4_msix->msix_count =3D ret; + + for (i =3D 0; i < MAX_HW_QUEUES; i++) + ae4->ae4_irq[i] =3D ae4_msix->msix_entry[i].vector; + + return 0; +} + +static int ae4_get_msi_irq(struct ae4_device *ae4) +{ + struct device *dev =3D ae4->dev; + struct pci_dev *pdev =3D to_pci_dev(dev); + int ret, i; + + ret =3D pci_enable_msi(pdev); + if (ret) + return ret; + + for (i =3D 0; i < MAX_HW_QUEUES; i++) + ae4->ae4_irq[i] =3D pdev->irq; + + return 0; +} + +static int ae4_get_irqs(struct ae4_device *ae4) +{ + struct device *dev =3D ae4->dev; + int ret; + + ret =3D ae4_get_msix_irqs(ae4); + if (!ret) + return 0; + + /* Couldn't get MSI-X vectors, try MSI */ + dev_err(dev, "could not enable MSI-X (%d), trying MSI\n", ret); + ret =3D ae4_get_msi_irq(ae4); + if (!ret) + return 0; + + /* Couldn't get MSI interrupt */ + dev_err(dev, "could not enable MSI (%d)\n", ret); + + return ret; +} + +static void ae4_free_irqs(struct ae4_device *ae4) +{ + struct ae4_msix *ae4_msix =3D ae4->ae4_msix; + struct device *dev =3D ae4->dev; + struct pci_dev *pdev =3D to_pci_dev(dev); + unsigned int i; + + if (ae4_msix->msix_count) + pci_disable_msix(pdev); + else if (ae4->ae4_irq) + pci_disable_msi(pdev); + + for (i =3D 0; i < MAX_HW_QUEUES; i++) + ae4->ae4_irq[i] =3D 0; +} + +static int ae4_pci_probe(struct pci_dev *pdev, const struct pci_device_id = *id) +{ + struct ae4_device *ae4; + struct ae4_msix *ae4_msix; + struct device *dev =3D &pdev->dev; + void __iomem * const *iomap_table; + int bar_mask; + int ret =3D -ENOMEM; + + ae4 =3D ae4_alloc_struct(dev); + if (!ae4) + goto e_err; + + ae4_msix =3D devm_kzalloc(dev, sizeof(*ae4_msix), GFP_KERNEL); + if (!ae4_msix) + goto e_err; + + ae4->ae4_msix =3D ae4_msix; + ae4->dev_vdata =3D (struct ae4_dev_vdata *)id->driver_data; + if (!ae4->dev_vdata) { + ret =3D -ENODEV; + dev_err(dev, "missing driver data\n"); + goto e_err; + } + + ret =3D pcim_enable_device(pdev); + if (ret) { + dev_err(dev, "pcim_enable_device failed (%d)\n", ret); + goto e_err; + } + + bar_mask =3D pci_select_bars(pdev, IORESOURCE_MEM); + ret =3D pcim_iomap_regions(pdev, bar_mask, "ae4dma"); + if (ret) { + dev_err(dev, "pcim_iomap_regions failed (%d)\n", ret); + goto e_err; + } + + iomap_table =3D pcim_iomap_table(pdev); + if (!iomap_table) { + dev_err(dev, "pcim_iomap_table failed\n"); + ret =3D -ENOMEM; + goto e_err; + } + + ae4->io_regs =3D iomap_table[ae4->dev_vdata->bar]; + if (!ae4->io_regs) { + dev_err(dev, "ioremap failed\n"); + ret =3D -ENOMEM; + goto e_err; + } + + ret =3D ae4_get_irqs(ae4); + if (ret) + goto e_err; + + pci_set_master(pdev); + + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); + if (ret) { + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", + ret); + goto e_err; + } + } + + dev_set_drvdata(dev, ae4); + + if (ae4->dev_vdata) + ret =3D ae4_core_init(ae4); + + if (ret) + goto e_err; + + return 0; + +e_err: + dev_err(dev, "initialization failed ret =3D %d\n", ret); + + return ret; +} + +static void ae4_pci_remove(struct pci_dev *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ae4_device *ae4 =3D dev_get_drvdata(dev); + + if (!ae4) + return; + + if (ae4->dev_vdata) + ae4_core_destroy(ae4); + + ae4_free_irqs(ae4); +} + +static const struct ae4_dev_vdata dev_vdata[] =3D { + { + .bar =3D 0, + }, +}; + +static const struct pci_device_id ae4_pci_table[] =3D { + { PCI_VDEVICE(AMD, 0x14C8), (kernel_ulong_t)&dev_vdata[0] }, + { PCI_VDEVICE(AMD, 0x14DC), (kernel_ulong_t)&dev_vdata[0] }, + /* Last entry must be zero */ + { 0, } +}; +MODULE_DEVICE_TABLE(pci, ae4_pci_table); + +static struct pci_driver ae4_pci_driver =3D { + .name =3D "ae4dma", + .id_table =3D ae4_pci_table, + .probe =3D ae4_pci_probe, + .remove =3D ae4_pci_remove, +}; + +module_pci_driver(ae4_pci_driver); + +MODULE_AUTHOR("Sanjay R Mehta "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("AMD AE4DMA driver"); diff --git a/drivers/dma/ae4dma/ae4dma.h b/drivers/dma/ae4dma/ae4dma.h new file mode 100644 index 0000000..0ae46ee --- /dev/null +++ b/drivers/dma/ae4dma/ae4dma.h @@ -0,0 +1,338 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AMD AE4DMA device driver + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Sanjay R Mehta + */ + +#ifndef __AE4_DEV_H__ +#define __AE4_DEV_H__ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_AE4_NAME_LEN 16 +#define MAX_DMAPOOL_NAME_LEN 32 + +#define MAX_HW_QUEUES 16 +#define MAX_CMD_QLEN 32 + +#define AE4_ENGINE_PASSTHRU 5 + +/* Register Mappings */ +#define IRQ_MASK_REG 0x040 +#define IRQ_STATUS_REG 0x200 + +#define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f) + +#define CMD_QUEUE_PRIO_OFFSET 0x00 +#define CMD_REQID_CONFIG_OFFSET 0x04 +#define CMD_TIMEOUT_OFFSET 0x08 +#define CMD_AE4_VERSION 0x10 + +#define CMD_Q_CONTROL_BASE 0x0000 +#define CMD_Q_TAIL_LO_BASE 0x0004 +#define CMD_Q_HEAD_LO_BASE 0x0008 +#define CMD_Q_INT_ENABLE_BASE 0x000C +#define CMD_Q_INTERRUPT_STATUS_BASE 0x0010 + +#define CMD_Q_STATUS_BASE 0x0100 +#define CMD_Q_INT_STATUS_BASE 0x0104 +#define CMD_Q_DMA_STATUS_BASE 0x0108 +#define CMD_Q_DMA_READ_STATUS_BASE 0x010C +#define CMD_Q_DMA_WRITE_STATUS_BASE 0x0110 +#define CMD_Q_ABORT_BASE 0x0114 +#define CMD_Q_AX_CACHE_BASE 0x0118 + +#define CMD_CONFIG_OFFSET 0x1120 +#define CMD_CLK_GATE_CTL_OFFSET 0x6004 + +#define CMD_DESC_DW0_VAL 0x000002 + +/* Address offset for virtual queue registers */ +#define CMD_Q_STATUS_INCR 0x1000 + +/* Bit masks */ +#define CMD_CONFIG_REQID 0 +#define CMD_TIMEOUT_DISABLE 0 +#define CMD_CLK_DYN_GATING_DIS 0 +#define CMD_CLK_SW_GATE_MODE 0 +#define CMD_CLK_GATE_CTL 0 +#define CMD_QUEUE_PRIO GENMASK(2, 1) +#define CMD_CONFIG_VHB_EN BIT(0) +#define CMD_CLK_DYN_GATING_EN BIT(0) +#define CMD_CLK_HW_GATE_MODE BIT(0) +#define CMD_CLK_GATE_ON_DELAY BIT(12) +#define CMD_CLK_GATE_OFF_DELAY BIT(12) + +#define CMD_CLK_GATE_CONFIG (CMD_CLK_GATE_CTL | \ + CMD_CLK_HW_GATE_MODE | \ + CMD_CLK_GATE_ON_DELAY | \ + CMD_CLK_DYN_GATING_EN | \ + CMD_CLK_GATE_OFF_DELAY) + +#define CMD_Q_LEN 32 +#define CMD_Q_RUN BIT(0) +#define CMD_Q_HALT BIT(1) +#define CMD_Q_MEM_LOCATION BIT(2) +#define CMD_Q_SIZE_MASK GENMASK(4, 0) +#define CMD_Q_SIZE GENMASK(7, 3) +#define CMD_Q_SHIFT GENMASK(1, 0) +#define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \ + CMD_Q_SIZE_MASK) +#define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1) +#define Q_DESC_SIZE sizeof(struct ae4dma_desc) +#define Q_SIZE(n) (CMD_Q_LEN * (n)) + +#define INT_DESC_VALIDATED BIT(1) +#define INT_DESC_PROCESSED BIT(2) +#define INT_COMPLETION BIT(3) +#define INT_ERROR BIT(4) + +#define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR) + +/****** Local Storage Block ******/ +#define LSB_START 0 +#define LSB_END 127 +#define LSB_COUNT (LSB_END - LSB_START + 1) + +#define AE4_DMAPOOL_MAX_SIZE 64 +#define AE4_DMAPOOL_ALIGN BIT(5) + +#define AE4_PASSTHRU_BLOCKSIZE 512 + +struct ae4_device; + +struct ae4_tasklet_data { + struct completion completion; + struct ae4_cmd *cmd; +}; + +/* + * struct ae4_passthru_engine - pass-through operation + * without performing DMA mapping + * @mask: mask to be applied to data + * @mask_len: length in bytes of mask + * @src_dma: data to be used for this operation + * @dst_dma: data produced by this operation + * @src_len: length in bytes of data used for this operation + * + * Variables required to be set when calling ae4_enqueue_cmd(): + * - bit_mod, byte_swap, src, dst, src_len + * - mask, mask_len if bit_mod is not AE4_PASSTHRU_BITWISE_NOOP + */ +struct ae4_passthru_engine { + dma_addr_t mask; + u32 mask_len; /* In bytes */ + + dma_addr_t src_dma, dst_dma; + u64 src_len; /* In bytes */ +}; + +/* + * struct ae4_cmd - AE4DMA operation request + * @entry: list element + * @work: work element used for callbacks + * @ae4: AE4 device to be run on + * @ret: operation return code + * @flags: cmd processing flags + * @engine: AE4DMA operation to perform (passthru) + * @engine_error: AE4 engine return code + * @passthru: engine specific structures, refer to specific engine struct = below + * @callback: operation completion callback function + * @data: parameter value to be supplied to the callback function + * + * Variables required to be set when calling ae4_enqueue_cmd(): + * - engine, callback + * - See the operation structures below for what is required for each + * operation. + */ +struct ae4_cmd { + struct list_head entry; + struct work_struct work; + struct ae4_device *ae4; + int ret; + u32 engine; + u32 engine_error; + struct ae4_passthru_engine passthru; + /* Completion callback support */ + void (*ae4_cmd_callback)(void *data, int err); + void *data; + u8 qid; +}; + +struct ae4_cmd_queue { + struct ae4_device *ae4; + + /* Queue identifier */ + u32 id; + + /* Queue dma pool */ + struct dma_pool *dma_pool; + + /* Queue base address (not neccessarily aligned)*/ + struct ae4dma_desc *qbase; + + /* Aligned queue start address (per requirement) */ + struct mutex q_mutex ____cacheline_aligned; + spinlock_t q_lock ____cacheline_aligned; + unsigned long qidx; + + unsigned int qsize; + dma_addr_t qbase_dma; + dma_addr_t qdma_tail; + + unsigned int active; + unsigned int suspended; + + /* Interrupt flag */ + bool int_en; + + /* Register addresses for queue */ + void __iomem *reg_control; + u32 qcontrol; /* Cached control register */ + + /* Status values from job */ + u32 int_status; + u32 q_status; + u32 q_int_status; + u32 cmd_error; + + /* Interrupt wait queue */ + wait_queue_head_t int_queue; + unsigned int int_rcvd; + + wait_queue_head_t q_space; + unsigned int q_space_available; + + struct ae4_tasklet_data tdata; + struct tasklet_struct irq_tasklet; + + struct list_head cmd; + spinlock_t cmd_lock ____cacheline_aligned; +} ____cacheline_aligned; + +struct ae4_device { + struct list_head entry; + + unsigned int ord; + char name[MAX_AE4_NAME_LEN]; + + struct device *dev; + + /* Bus specific device information */ + struct ae4_msix *ae4_msix; + + struct ae4_dev_vdata *dev_vdata; + + unsigned int ae4_irq[MAX_HW_QUEUES]; + + /* I/O area used for device communication */ + void __iomem *io_regs; + + spinlock_t cmd_lock ____cacheline_aligned; + unsigned int cmd_count; + struct list_head cmd; + + /* + * The command queue. This represent the queue available on the + * AE4DMA that are available for processing cmds + */ + struct ae4_cmd_queue cmd_q[MAX_HW_QUEUES]; + unsigned int cmd_q_count; + + wait_queue_head_t lsb_queue; +}; + +/* + * descriptor for AE4DMA commands + * 8 32-bit words: + * word 0: function; engine; control bits + * word 1: length of source data + * word 2: low 32 bits of source pointer + * word 3: upper 16 bits of source pointer; source memory type + * word 4: low 32 bits of destination pointer + * word 5: upper 16 bits of destination pointer; destination memory type + * word 6: reserved 32 bits + * word 7: reserved 32 bits + */ + +#define DWORD0_SOC BIT(0) +#define DWORD0_IOC BIT(1) +#define DWORD0_SOM BIT(3) +#define DWORD0_EOM BIT(4) +#define DWORD0_DMT GENMASK(5, 4) +#define DWORD0_SMT GENMASK(7, 6) + +#define DWORD0_DMT_MEM 0x0 +#define DWORD0_DMT_IO BIT(4) +#define DWORD0_SMT_MEM 0x0 +#define DWORD0_SMT_IO BIT(6) + +struct dword1 { + u8 status; + u8 err_code; + u16 desc_id; +}; + +struct ae4dma_desc { + u32 dw0; + struct dword1 dw1; + u32 length; + __le32 rsvd; + u32 src_hi; + u32 src_lo; + u32 dst_hi; + u32 dst_lo; +}; + +/* Structure to hold AE4 device data */ +struct ae4_dev_vdata { + const unsigned int bar; +}; + +int ae4_core_init(struct ae4_device *ae4); +void ae4_core_destroy(struct ae4_device *ae4); + +int ae4_core_perform_passthru(struct ae4_cmd_queue *cmd_q, + struct ae4_passthru_engine *ae4_engine); + +void ae4_check_status_trans(struct ae4_device *ae4, struct ae4_cmd_queue *= cmd_q); +void ae4_start_queue(struct ae4_cmd_queue *cmd_q); +void ae4_stop_queue(struct ae4_cmd_queue *cmd_q); + +static inline void ae4_core_disable_queue_interrupts(struct ae4_device *ae= 4, + struct ae4_cmd_queue *cmd_q) +{ + iowrite32(0, cmd_q->reg_control); +} + +static inline void ae4_core_enable_queue_interrupts(struct ae4_device *ae4, + struct ae4_cmd_queue *cmd_q) +{ + iowrite32(0X7, cmd_q->reg_control); +} + +static inline bool ae4_core_queue_full(struct ae4_device *ae4, struct ae4_= cmd_queue *cmd_q) +{ + u32 q_sts =3D ioread32(cmd_q->reg_control + 0x4) & 0x06; + + u32 rear_ri =3D ioread32(cmd_q->reg_control + 0x0C); + u32 front_wi =3D ioread32(cmd_q->reg_control + 0x10); + + q_sts >>=3D 1; + + if (((MAX_CMD_QLEN + front_wi - rear_ri) % MAX_CMD_QLEN) >=3D (MAX_CMD_Q= LEN - 1)) + return true; + + return false; +} + +#endif --=20 2.7.4 From nobody Sun Feb 8 12:43:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F4A4CA0EC3 for ; Mon, 11 Sep 2023 21:26:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236082AbjIKVRp (ORCPT ); Mon, 11 Sep 2023 17:17:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244168AbjIKTZy (ORCPT ); Mon, 11 Sep 2023 15:25:54 -0400 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2076.outbound.protection.outlook.com [40.107.95.76]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CC4C10F; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2023 19:25:45.8286 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b96d959-8956-4b09-839c-08dbb2fce5c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8775 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sanjay R Mehta Register ae4dma queue's to Linux dmaengine framework as general-purpose DMA channels. Signed-off-by: Sanjay R Mehta --- drivers/dma/ae4dma/Kconfig | 2 + drivers/dma/ae4dma/Makefile | 2 +- drivers/dma/ae4dma/ae4dma-dev.c | 17 ++ drivers/dma/ae4dma/ae4dma-dmaengine.c | 425 ++++++++++++++++++++++++++++++= ++++ drivers/dma/ae4dma/ae4dma.h | 28 +++ 5 files changed, 473 insertions(+), 1 deletion(-) create mode 100644 drivers/dma/ae4dma/ae4dma-dmaengine.c diff --git a/drivers/dma/ae4dma/Kconfig b/drivers/dma/ae4dma/Kconfig index 1cda9de..3d1dbb7 100644 --- a/drivers/dma/ae4dma/Kconfig +++ b/drivers/dma/ae4dma/Kconfig @@ -2,6 +2,8 @@ config AMD_AE4DMA tristate "AMD AE4DMA Engine" depends on X86_64 && PCI + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS help Enabling this option provides support for the AMD AE4DMA controller, which offers DMA capabilities for high-bandwidth memory-to-memory and diff --git a/drivers/dma/ae4dma/Makefile b/drivers/dma/ae4dma/Makefile index db9cab1..b1e4318 100644 --- a/drivers/dma/ae4dma/Makefile +++ b/drivers/dma/ae4dma/Makefile @@ -5,6 +5,6 @@ =20 obj-$(CONFIG_AMD_AE4DMA) +=3D ae4dma.o =20 -ae4dma-objs :=3D ae4dma-dev.o +ae4dma-objs :=3D ae4dma-dev.o ae4dma-dmaengine.o =20 ae4dma-$(CONFIG_PCI) +=3D ae4dma-pci.o diff --git a/drivers/dma/ae4dma/ae4dma-dev.c b/drivers/dma/ae4dma/ae4dma-de= v.c index a3c50a2..af7e510 100644 --- a/drivers/dma/ae4dma/ae4dma-dev.c +++ b/drivers/dma/ae4dma/ae4dma-dev.c @@ -25,6 +25,11 @@ static unsigned int max_hw_q =3D 1; module_param(max_hw_q, uint, 0444); MODULE_PARM_DESC(max_hw_q, "Max queues per engine (any non-zero value less= than or equal to 16, default: 1)"); =20 +static inline struct ae4_dma_chan *to_ae4_chan(struct dma_chan *dma_chan) +{ + return container_of(dma_chan, struct ae4_dma_chan, vc.chan); +} + /* Human-readable error strings */ static char *ae4_error_codes[] =3D { "", @@ -273,8 +278,17 @@ int ae4_core_init(struct ae4_device *ae4) tasklet_setup(&cmd_q->irq_tasklet, ae4_do_cmd_complete); } =20 + /* register to the DMA engine */ + ret =3D ae4_dmaengine_register(ae4); + if (ret) + goto e_free_irq; + return 0; =20 +e_free_irq: + for (i =3D 0; i < ae4->cmd_q_count; i++) + free_irq(ae4->ae4_irq[i], ae4); + e_free_dma: dma_free_coherent(dev, cmd_q->qsize, cmd_q->qbase, cmd_q->qbase_dma); =20 @@ -292,6 +306,9 @@ void ae4_core_destroy(struct ae4_device *ae4) struct ae4_cmd *cmd; unsigned int i; =20 + /* Unregister the DMA engine */ + ae4_dmaengine_unregister(ae4); + for (i =3D 0; i < ae4->cmd_q_count; i++) { cmd_q =3D &ae4->cmd_q[i]; =20 diff --git a/drivers/dma/ae4dma/ae4dma-dmaengine.c b/drivers/dma/ae4dma/ae4= dma-dmaengine.c new file mode 100644 index 0000000..a50e4f5 --- /dev/null +++ b/drivers/dma/ae4dma/ae4dma-dmaengine.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD AE4DMA device driver + * -- Based on the PTDMA driver + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Sanjay R Mehta + */ +#include +#include "ae4dma.h" +#include "../dmaengine.h" +#include "../virt-dma.h" + +static inline struct ae4_dma_chan *to_ae4_chan(struct dma_chan *dma_chan) +{ + return container_of(dma_chan, struct ae4_dma_chan, vc.chan); +} + +static inline struct ae4_dma_desc *to_ae4_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct ae4_dma_desc, vd); +} + +static void ae4_free_chan_resources(struct dma_chan *dma_chan) +{ + struct ae4_dma_chan *chan =3D to_ae4_chan(dma_chan); + + vchan_free_chan_resources(&chan->vc); +} + +static void ae4_synchronize(struct dma_chan *dma_chan) +{ + struct ae4_dma_chan *chan =3D to_ae4_chan(dma_chan); + + vchan_synchronize(&chan->vc); +} + +static void ae4_do_cleanup(struct virt_dma_desc *vd) +{ + struct ae4_dma_desc *desc =3D to_ae4_desc(vd); + struct ae4_device *ae4 =3D desc->ae4; + + kmem_cache_free(ae4->dma_desc_cache, desc); +} + +static int ae4_dma_start_desc(struct ae4_dma_desc *desc, struct ae4_dma_ch= an *chan) +{ + struct ae4_passthru_engine *ae4_engine; + struct ae4_device *ae4; + struct ae4_cmd *ae4_cmd; + struct ae4_cmd_queue *cmd_q; + + desc->issued_to_hw =3D 1; + list_del(&desc->vd.node); + + ae4_cmd =3D &desc->ae4_cmd; + ae4 =3D ae4_cmd->ae4; + cmd_q =3D chan->cmd_q; + ae4_engine =3D &ae4_cmd->passthru; + + ae4_cmd->qid =3D cmd_q->qidx; + cmd_q->tdata.cmd =3D ae4_cmd; + + /* Execute the command */ + ae4_cmd->ret =3D ae4_core_perform_passthru(cmd_q, ae4_engine); + + return 0; +} + +static struct ae4_dma_desc *ae4_next_dma_desc(struct ae4_dma_chan *chan) +{ + /* Get the next DMA descriptor on the active list */ + struct virt_dma_desc *vd =3D vchan_next_desc(&chan->vc); + + return vd ? to_ae4_desc(vd) : NULL; +} + +static void ae4_cmd_callback_tasklet(void *data, int err) +{ + struct ae4_dma_desc *desc =3D data; + struct dma_chan *dma_chan; + struct ae4_dma_chan *chan; + struct dma_async_tx_descriptor *tx_desc; + struct virt_dma_desc *vd; + unsigned long flags; + + dma_chan =3D desc->vd.tx.chan; + chan =3D to_ae4_chan(dma_chan); + + if (err =3D=3D -EINPROGRESS) + return; + + tx_desc =3D &desc->vd.tx; + vd =3D &desc->vd; + + if (err) + desc->status =3D DMA_ERROR; + + spin_lock_irqsave(&chan->vc.lock, flags); + if (desc) { + if (desc->status !=3D DMA_COMPLETE) { + if (desc->status !=3D DMA_ERROR) + desc->status =3D DMA_COMPLETE; + + dma_cookie_complete(tx_desc); + dma_descriptor_unmap(tx_desc); + } else { + /* Don't handle it twice */ + tx_desc =3D NULL; + } + } + spin_unlock_irqrestore(&chan->vc.lock, flags); + + if (tx_desc) { + dmaengine_desc_get_callback_invoke(tx_desc, NULL); + dma_run_dependencies(tx_desc); + } +} + +static struct ae4_dma_desc *ae4_handle_active_desc(struct ae4_dma_chan *ch= an, + struct ae4_dma_desc *desc) +{ + struct dma_async_tx_descriptor *tx_desc; + struct virt_dma_desc *vd; + unsigned long flags; + + /* Loop over descriptors until one is found with commands */ + do { + if (desc) { + if (!desc->issued_to_hw) { + /* No errors, keep going */ + if (desc->status !=3D DMA_ERROR) + return desc; + } + tx_desc =3D &desc->vd.tx; + vd =3D &desc->vd; + } else { + tx_desc =3D NULL; + } + spin_lock_irqsave(&chan->vc.lock, flags); + desc =3D ae4_next_dma_desc(chan); + spin_unlock_irqrestore(&chan->vc.lock, flags); + } while (desc); + + return NULL; +} + +static void ae4_cmd_callback(void *data, int err) +{ + struct ae4_dma_desc *desc =3D data; + struct dma_chan *dma_chan; + struct ae4_dma_chan *chan; + struct ae4_device *ae4; + int ret; + + if (err =3D=3D -EINPROGRESS) + return; + + dma_chan =3D desc->vd.tx.chan; + chan =3D to_ae4_chan(dma_chan); + ae4 =3D chan->ae4; + + if (err) + desc->status =3D DMA_ERROR; + + while (true) { + /* Check for DMA descriptor completion */ + desc =3D ae4_handle_active_desc(chan, desc); + + /* Don't submit cmd if no descriptor or DMA is paused */ + if (!desc) + break; + + /* if queue is full dont submit to queue */ + if (ae4_core_queue_full(ae4, chan->cmd_q)) { + usleep_range(100, 200); + continue; + } + + ret =3D ae4_dma_start_desc(desc, chan); + if (!ret) + break; + + desc->status =3D DMA_ERROR; + } +} + +static struct ae4_dma_desc *ae4_alloc_dma_desc(struct ae4_dma_chan *chan, = unsigned long flags) +{ + struct ae4_dma_desc *desc; + struct ae4_cmd_queue *cmd_q =3D chan->cmd_q; + + desc =3D kmem_cache_zalloc(chan->ae4->dma_desc_cache, GFP_NOWAIT); + if (!desc) + return NULL; + + vchan_tx_prep(&chan->vc, &desc->vd, flags); + + desc->ae4 =3D chan->ae4; + cmd_q->int_en =3D !!(flags & DMA_PREP_INTERRUPT); + desc->issued_to_hw =3D 0; + desc->status =3D DMA_IN_PROGRESS; + + return desc; +} + +static struct ae4_dma_desc *ae4_create_desc(struct dma_chan *dma_chan, + dma_addr_t dst, + dma_addr_t src, + unsigned int len, + unsigned long flags) +{ + struct ae4_dma_chan *chan =3D to_ae4_chan(dma_chan); + struct ae4_cmd_queue *cmd_q =3D chan->cmd_q; + struct ae4_passthru_engine *ae4_engine; + struct ae4_dma_desc *desc; + struct ae4_cmd *ae4_cmd; + + desc =3D ae4_alloc_dma_desc(chan, flags); + if (!desc) + return NULL; + + ae4_cmd =3D &desc->ae4_cmd; + ae4_cmd->ae4 =3D chan->ae4; + ae4_engine =3D &ae4_cmd->passthru; + ae4_cmd->engine =3D AE4_ENGINE_PASSTHRU; + ae4_engine->src_dma =3D src; + ae4_engine->dst_dma =3D dst; + ae4_engine->src_len =3D len; + ae4_cmd->ae4_cmd_callback =3D ae4_cmd_callback_tasklet; + ae4_cmd->data =3D desc; + + desc->len =3D len; + + spin_lock_irqsave(&cmd_q->cmd_lock, flags); + list_add_tail(&ae4_cmd->entry, &cmd_q->cmd); + spin_unlock_irqrestore(&cmd_q->cmd_lock, flags); + + return desc; +} + +static struct dma_async_tx_descriptor * +ae4_prep_dma_memcpy(struct dma_chan *dma_chan, dma_addr_t dst, + dma_addr_t src, size_t len, unsigned long flags) +{ + struct ae4_dma_desc *desc; + + desc =3D ae4_create_desc(dma_chan, dst, src, len, flags); + if (!desc) + return NULL; + + return &desc->vd.tx; +} + +static struct dma_async_tx_descriptor * +ae4_prep_dma_interrupt(struct dma_chan *dma_chan, unsigned long flags) +{ + struct ae4_dma_chan *chan =3D to_ae4_chan(dma_chan); + struct ae4_dma_desc *desc; + + desc =3D ae4_alloc_dma_desc(chan, flags); + if (!desc) + return NULL; + + return &desc->vd.tx; +} + +static void ae4_issue_pending(struct dma_chan *dma_chan) +{ + struct ae4_dma_chan *chan =3D to_ae4_chan(dma_chan); + struct ae4_dma_desc *desc; + unsigned long flags; + + spin_lock_irqsave(&chan->vc.lock, flags); + vchan_issue_pending(&chan->vc); + desc =3D ae4_next_dma_desc(chan); + spin_unlock_irqrestore(&chan->vc.lock, flags); + + ae4_cmd_callback(desc, 0); +} + +static int ae4_pause(struct dma_chan *dma_chan) +{ + struct ae4_dma_chan *chan =3D to_ae4_chan(dma_chan); + unsigned long flags; + + spin_lock_irqsave(&chan->vc.lock, flags); + //TODO : implemnt pause + spin_unlock_irqrestore(&chan->vc.lock, flags); + + return 0; +} + +static int ae4_resume(struct dma_chan *dma_chan) +{ + struct ae4_dma_chan *chan =3D to_ae4_chan(dma_chan); + struct ae4_dma_desc *desc =3D NULL; + unsigned long flags; + + spin_lock_irqsave(&chan->vc.lock, flags); + ae4_start_queue(chan->cmd_q); + desc =3D ae4_next_dma_desc(chan); + spin_unlock_irqrestore(&chan->vc.lock, flags); + + /* If there was something active, re-start */ + if (desc) + ae4_cmd_callback(desc, 0); + + return 0; +} + +static int ae4_terminate_all(struct dma_chan *dma_chan) +{ + struct ae4_dma_chan *chan =3D to_ae4_chan(dma_chan); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&chan->vc.lock, flags); + vchan_get_all_descriptors(&chan->vc, &head); + spin_unlock_irqrestore(&chan->vc.lock, flags); + + vchan_dma_desc_free_list(&chan->vc, &head); + vchan_free_chan_resources(&chan->vc); + + return 0; +} + +int ae4_dmaengine_register(struct ae4_device *ae4) +{ + struct ae4_dma_chan *chan; + struct ae4_cmd_queue *cmd_q; + struct dma_device *dma_dev =3D &ae4->dma_dev; + char *cmd_cache_name; + char *desc_cache_name; + unsigned int i; + int ret; + + ae4->ae4_dma_chan =3D devm_kcalloc(ae4->dev, ae4->cmd_q_count, + sizeof(*ae4->ae4_dma_chan), GFP_KERNEL); + if (!ae4->ae4_dma_chan) + return -ENOMEM; + + cmd_cache_name =3D devm_kasprintf(ae4->dev, GFP_KERNEL, + "%s-dmaengine-cmd-cache", + dev_name(ae4->dev)); + if (!cmd_cache_name) + return -ENOMEM; + + desc_cache_name =3D devm_kasprintf(ae4->dev, GFP_KERNEL, + "%s-dmaengine-desc-cache", + dev_name(ae4->dev)); + if (!desc_cache_name) { + ret =3D -ENOMEM; + goto err_cache; + } + + ae4->dma_desc_cache =3D kmem_cache_create(desc_cache_name, + sizeof(struct ae4_dma_desc), 0, + SLAB_HWCACHE_ALIGN, NULL); + if (!ae4->dma_desc_cache) { + ret =3D -ENOMEM; + goto err_cache; + } + + dma_dev->dev =3D ae4->dev; + dma_dev->src_addr_widths =3D DMA_SLAVE_BUSWIDTH_64_BYTES; + dma_dev->dst_addr_widths =3D DMA_SLAVE_BUSWIDTH_64_BYTES; + dma_dev->directions =3D DMA_MEM_TO_MEM; + dma_dev->residue_granularity =3D DMA_RESIDUE_GRANULARITY_DESCRIPTOR; + dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); + dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask); + + /* + * AE4DMA is intended to be used with the AMD NTB devices, hence + * marking it as DMA_PRIVATE. + */ + dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask); + + /* Set base and prep routines */ + dma_dev->device_free_chan_resources =3D ae4_free_chan_resources; + dma_dev->device_prep_dma_memcpy =3D ae4_prep_dma_memcpy; + dma_dev->device_prep_dma_interrupt =3D ae4_prep_dma_interrupt; + dma_dev->device_issue_pending =3D ae4_issue_pending; + dma_dev->device_tx_status =3D dma_cookie_status; + dma_dev->device_pause =3D ae4_pause; + dma_dev->device_resume =3D ae4_resume; + dma_dev->device_terminate_all =3D ae4_terminate_all; + dma_dev->device_synchronize =3D ae4_synchronize; + + INIT_LIST_HEAD(&dma_dev->channels); + for (i =3D 0; i < ae4->cmd_q_count; i++) { + chan =3D ae4->ae4_dma_chan + i; + cmd_q =3D &ae4->cmd_q[i]; + chan->cmd_q =3D cmd_q; + chan->id =3D cmd_q->id; + chan->ae4 =3D ae4; + chan->vc.desc_free =3D ae4_do_cleanup; + vchan_init(&chan->vc, dma_dev); + } + + dma_set_mask_and_coherent(ae4->dev, DMA_BIT_MASK(64)); + + ret =3D dma_async_device_register(dma_dev); + if (ret) + goto err_reg; + + return 0; + +err_reg: + kmem_cache_destroy(ae4->dma_desc_cache); + +err_cache: + kmem_cache_destroy(ae4->dma_cmd_cache); + + return ret; +} + +void ae4_dmaengine_unregister(struct ae4_device *ae4) +{ + struct dma_device *dma_dev =3D &ae4->dma_dev; + + dma_async_device_unregister(dma_dev); + kmem_cache_destroy(ae4->dma_cmd_cache); +} diff --git a/drivers/dma/ae4dma/ae4dma.h b/drivers/dma/ae4dma/ae4dma.h index 0ae46ee..d341c35 100644 --- a/drivers/dma/ae4dma/ae4dma.h +++ b/drivers/dma/ae4dma/ae4dma.h @@ -11,6 +11,7 @@ #define __AE4_DEV_H__ =20 #include +#include #include #include #include @@ -18,6 +19,8 @@ #include #include =20 +#include "../virt-dma.h" + #define MAX_AE4_NAME_LEN 16 #define MAX_DMAPOOL_NAME_LEN 32 =20 @@ -168,6 +171,22 @@ struct ae4_cmd { u8 qid; }; =20 +struct ae4_dma_desc { + struct virt_dma_desc vd; + struct ae4_device *ae4; + enum dma_status status; + size_t len; + bool issued_to_hw; + struct ae4_cmd ae4_cmd; +}; + +struct ae4_dma_chan { + struct virt_dma_chan vc; + struct ae4_device *ae4; + struct ae4_cmd_queue *cmd_q; + u32 id; +}; + struct ae4_cmd_queue { struct ae4_device *ae4; =20 @@ -248,6 +267,12 @@ struct ae4_device { struct ae4_cmd_queue cmd_q[MAX_HW_QUEUES]; unsigned int cmd_q_count; =20 + /* Support for the DMA Engine capabilities */ + struct dma_device dma_dev; + struct ae4_dma_chan *ae4_dma_chan; + struct kmem_cache *dma_cmd_cache; + struct kmem_cache *dma_desc_cache; + wait_queue_head_t lsb_queue; }; =20 @@ -298,6 +323,9 @@ struct ae4_dev_vdata { const unsigned int bar; }; =20 +int ae4_dmaengine_register(struct ae4_device *ae4); +void ae4_dmaengine_unregister(struct ae4_device *ae4); + int ae4_core_init(struct ae4_device *ae4); void ae4_core_destroy(struct ae4_device *ae4); =20 --=20 2.7.4 From nobody Sun Feb 8 12:43:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C84F6EE3F07 for ; Mon, 11 Sep 2023 20:50:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231458AbjIKUub (ORCPT ); Mon, 11 Sep 2023 16:50:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244171AbjIKTZ6 (ORCPT ); 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Mon, 11 Sep 2023 14:25:45 -0500 From: Sanjay R Mehta To: CC: , , , , , , , Sanjay R Mehta Subject: [PATCH 3/3] dmaengine: ae4dma: Add debugfs entries for AE4DMA Date: Mon, 11 Sep 2023 14:25:24 -0500 Message-ID: <1694460324-60346-4-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1694460324-60346-1-git-send-email-Sanju.Mehta@amd.com> References: <1694460324-60346-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|SA3PR12MB7832:EE_ X-MS-Office365-Filtering-Correlation-Id: 192f2d02-496c-4599-e482-08dbb2fce7a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GJe76Gs3rj4f/17n4lO9fv6+dNmXgogBgBwic1yZpZPnrYiTSXLauWT41m1kSK1S07w1Wa5ulFhjywmmOyFDQzWsqttwWWjjcAHufFA+xsyvaPoajJ2cEH3Ljjhk6MQhKhQ4d0XUX4YlOifiySYgNmlpgqbdYwbWaxpvOX4qOKFBK2/W+YQHW5d+iCSTOtTNz0goIhWSju0mucSbECn45A9eVdDTLi4qzCdSKITW9gXJw5jY+wuu3HWNhFJrwOVjQIZ1l2BcflumswdZ8QjatiDeRofEN0mAsoLR5GO/BgaD/qotnjqTIrHpc6z99uLBxTfZWlQe+R3Iy3Vr5k6xS6ibNOvnSJ2rORhnFP8DZJV7J8qPWlbWCwYXBVuVt4CWE8VBvI03/gzjuctIMxpAdDQgFO/GWJML73B3YeiKnoFiKcJY9ClJYVP+NMF5sdmKVZ4OJ37qa4OWDNJxpDBTm+j6f5HRKqWuu5psbrtzTFetsGHnRsTbaCRcglgWpVHuk33+nn/XDWvZFnIlY8ELay217nOMUX6nmurbcOtG+z9tzR4L1PIlQ3bp7wblLf9fBNuxRHlONUo621yzoRfm4K38vBcN+mT6swoRp/kPygBdswMXYrpWEApXCQYsvH+/Fvc2PsAgskBEDmeA/+xPD2fCeceaE1y5n+/ti4NFD3bcpjqRx/FnMc10/4qhEQ6T4xOrY5R0r0/q3NbUlqP9a+c7m6MTFIck1WfTjAHyDY699Y4GG2cdAv0BEpCx7en8A9nLnedYcM9rc9vHp06wsjrZMCFdMsDQlkiGSbMgHzQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(136003)(39860400002)(396003)(82310400011)(186009)(1800799009)(451199024)(40470700004)(36840700001)(46966006)(40460700003)(7696005)(6666004)(83380400001)(356005)(82740400003)(81166007)(86362001)(36860700001)(47076005)(36756003)(2616005)(336012)(426003)(16526019)(40480700001)(26005)(6916009)(316002)(41300700001)(2906002)(8936002)(70586007)(54906003)(70206006)(8676002)(4326008)(478600001)(5660300002)(32563001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2023 19:25:49.0162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 192f2d02-496c-4599-e482-08dbb2fce7a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7832 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sanjay R Mehta Expose data about the configuration and operation of the AE4DMA through debugfs entries: device name, capabilities, configuration, statistics. Signed-off-by: Sanjay R Mehta --- drivers/dma/ae4dma/Makefile | 2 +- drivers/dma/ae4dma/ae4dma-debugfs.c | 98 +++++++++++++++++++++++++++++++++= ++++ drivers/dma/ae4dma/ae4dma-dev.c | 16 ++++++ drivers/dma/ae4dma/ae4dma.h | 8 +++ 4 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 drivers/dma/ae4dma/ae4dma-debugfs.c diff --git a/drivers/dma/ae4dma/Makefile b/drivers/dma/ae4dma/Makefile index b1e4318..4082fec 100644 --- a/drivers/dma/ae4dma/Makefile +++ b/drivers/dma/ae4dma/Makefile @@ -5,6 +5,6 @@ =20 obj-$(CONFIG_AMD_AE4DMA) +=3D ae4dma.o =20 -ae4dma-objs :=3D ae4dma-dev.o ae4dma-dmaengine.o +ae4dma-objs :=3D ae4dma-dev.o ae4dma-dmaengine.o ae4dma-debugfs.o =20 ae4dma-$(CONFIG_PCI) +=3D ae4dma-pci.o diff --git a/drivers/dma/ae4dma/ae4dma-debugfs.c b/drivers/dma/ae4dma/ae4dm= a-debugfs.c new file mode 100644 index 0000000..ae6ec7d --- /dev/null +++ b/drivers/dma/ae4dma/ae4dma-debugfs.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD AE4DMA device driver + * -- Based on the PTDMA driver + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Sanjay R Mehta + */ + +#include +#include + +#include "ae4dma.h" + +/* DebugFS helpers */ +#define RI_VERSION_NUM 0x0000003F + +#define RI_NUM_VQM 0x00078000 +#define RI_NVQM_SHIFT 15 + +static int ae4_debugfs_info_show(struct seq_file *s, void *p) +{ + struct ae4_device *ae4 =3D s->private; + unsigned int regval; + + seq_printf(s, "Device name: %s\n", dev_name(ae4->dev)); + seq_printf(s, " # Queues: %d\n", 1); + seq_printf(s, " # Cmds: %d\n", ae4->cmd_count); + + regval =3D ioread32(ae4->io_regs + CMD_AE4_VERSION); + + seq_printf(s, " Version: %d\n", regval & RI_VERSION_NUM); + seq_puts(s, " Engines:"); + seq_puts(s, "\n"); + seq_printf(s, " Queues: %d\n", (regval & RI_NUM_VQM) >> RI_NVQM_SHIFT= ); + + return 0; +} + +/* + * Return a formatted buffer containing the current + * statistics of queue for AE4DMA + */ +static int ae4_debugfs_stats_show(struct seq_file *s, void *p) +{ + struct ae4_device *ae4 =3D s->private; + + seq_printf(s, "Total Interrupts Handled: %ld\n", ae4->total_interrupts); + + return 0; +} + +static int ae4_debugfs_queue_show(struct seq_file *s, void *p) +{ + struct ae4_cmd_queue *cmd_q =3D s->private; + + if (!cmd_q) + return 0; + + seq_printf(s, " Total CMDs submitted: %ld\n", cmd_q->total_ae4_ops= ); + seq_printf(s, " Total CMDs in q%d: %ld\n", cmd_q->id, cmd_q->q_cmd= _count); + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(ae4_debugfs_info); +DEFINE_SHOW_ATTRIBUTE(ae4_debugfs_queue); +DEFINE_SHOW_ATTRIBUTE(ae4_debugfs_stats); + +void ae4dma_debugfs_setup(struct ae4_device *ae4) +{ + struct ae4_cmd_queue *cmd_q; + struct dentry *debugfs_q_instance; + unsigned int i; + char name[30]; + + if (!debugfs_initialized()) + return; + + debugfs_create_file("info", 0400, ae4->dma_dev.dbg_dev_root, ae4, + &ae4_debugfs_info_fops); + + debugfs_create_file("stats", 0400, ae4->dma_dev.dbg_dev_root, ae4, + &ae4_debugfs_stats_fops); + + for (i =3D 0; i < ae4->cmd_q_count; i++) { + cmd_q =3D &ae4->cmd_q[i]; + + snprintf(name, 29, "q%d", cmd_q->id); + + debugfs_q_instance =3D + debugfs_create_dir(name, ae4->dma_dev.dbg_dev_root); + + debugfs_create_file("stats", 0400, debugfs_q_instance, cmd_q, + &ae4_debugfs_queue_fops); + } +} diff --git a/drivers/dma/ae4dma/ae4dma-dev.c b/drivers/dma/ae4dma/ae4dma-de= v.c index af7e510..fe5af0c0 100644 --- a/drivers/dma/ae4dma/ae4dma-dev.c +++ b/drivers/dma/ae4dma/ae4dma-dev.c @@ -74,6 +74,7 @@ static int ae4_core_execute_cmd(struct ae4dma_desc *desc,= struct ae4_cmd_queue * { bool soc =3D FIELD_GET(DWORD0_SOC, desc->dw0); u8 *q_desc =3D (u8 *)&cmd_q->qbase[0]; + unsigned long flags; u32 tail_wi; =20 cmd_q->int_rcvd =3D 0; @@ -99,6 +100,10 @@ static int ae4_core_execute_cmd(struct ae4dma_desc *des= c, struct ae4_cmd_queue * tail_wi =3D (tail_wi + 1) % CMD_Q_LEN; iowrite32(tail_wi, cmd_q->reg_control + 0x10); =20 + spin_lock_irqsave(&cmd_q->cmd_lock, flags); + cmd_q->q_cmd_count++; + spin_unlock_irqrestore(&cmd_q->cmd_lock, flags); + mutex_unlock(&cmd_q->q_mutex); =20 return 0; @@ -110,6 +115,7 @@ int ae4_core_perform_passthru(struct ae4_cmd_queue *cmd= _q, struct ae4_passthru_e struct ae4_device *ae4 =3D cmd_q->ae4; =20 cmd_q->cmd_error =3D 0; + cmd_q->total_ae4_ops++; memset(&desc, 0, sizeof(desc)); desc.dw0 =3D CMD_DESC_DW0_VAL; desc.dw1.status =3D 0; @@ -173,9 +179,12 @@ static irqreturn_t ae4_core_irq_handler(int irq, void = *data) { struct ae4_cmd_queue *cmd_q =3D data; struct ae4_device *ae4 =3D cmd_q->ae4; + unsigned long flags; u32 status =3D ioread32(cmd_q->reg_control + 0x4); u8 q_intr_type =3D (status >> 24) & 0xf; =20 + ae4->total_interrupts++; + if (q_intr_type =3D=3D 0x4) dev_info(ae4->dev, "AE4DMA INTR: %s (0x%x)\n", "queue desc error", q_int= r_type); else if (q_intr_type =3D=3D 0x2) @@ -187,6 +196,10 @@ static irqreturn_t ae4_core_irq_handler(int irq, void = *data) =20 ae4_check_status_trans(ae4, cmd_q); =20 + spin_lock_irqsave(&cmd_q->cmd_lock, flags); + cmd_q->q_cmd_count--; + spin_unlock_irqrestore(&cmd_q->cmd_lock, flags); + tasklet_schedule(&cmd_q->irq_tasklet); =20 return IRQ_HANDLED; @@ -283,6 +296,9 @@ int ae4_core_init(struct ae4_device *ae4) if (ret) goto e_free_irq; =20 + /* Set up debugfs entries */ + ae4dma_debugfs_setup(ae4); + return 0; =20 e_free_irq: diff --git a/drivers/dma/ae4dma/ae4dma.h b/drivers/dma/ae4dma/ae4dma.h index d341c35..ae31b26 100644 --- a/drivers/dma/ae4dma/ae4dma.h +++ b/drivers/dma/ae4dma/ae4dma.h @@ -231,6 +231,10 @@ struct ae4_cmd_queue { wait_queue_head_t q_space; unsigned int q_space_available; =20 + /* Queue Statistics */ + unsigned long total_ae4_ops; + unsigned long q_cmd_count; + struct ae4_tasklet_data tdata; struct tasklet_struct irq_tasklet; =20 @@ -274,6 +278,9 @@ struct ae4_device { struct kmem_cache *dma_desc_cache; =20 wait_queue_head_t lsb_queue; + + /* Device Statistics */ + unsigned long total_interrupts; }; =20 /* @@ -326,6 +333,7 @@ struct ae4_dev_vdata { int ae4_dmaengine_register(struct ae4_device *ae4); void ae4_dmaengine_unregister(struct ae4_device *ae4); =20 +void ae4dma_debugfs_setup(struct ae4_device *ae4); int ae4_core_init(struct ae4_device *ae4); void ae4_core_destroy(struct ae4_device *ae4); =20 --=20 2.7.4